Re: [PATCH] gpio: rockchip: restore interrupt settings after hibernation

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] gpio: rockchip: lost edge interrupts in rockchip_irq_resume()
  on GPIO v1
--

commit ee188794739447af06471d0bb656d9e9f704358d
Author: Igor Velkov <iav@iav.lv>

gpio: rockchip: restore interrupt settings after hibernation

This commit saves the GPIO interrupt enable, type, polarity, and both-edge
registers on suspend and restores them on resume so interrupt configuration
is preserved across hibernation.

> diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
> index 0f46ff095a248..83a5cc8f3fe68 100644
> --- a/drivers/gpio/gpio-rockchip.c
> +++ b/drivers/gpio/gpio-rockchip.c
> @@ -489,6 +489,11 @@ static void rockchip_irq_suspend(struct irq_data *d)
>  	struct rockchip_pin_bank *bank = gc->private;
>  
>  	bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
> +	bank->saved_en = rockchip_gpio_readl(bank, bank->gpio_regs->int_en);
> +	bank->saved_type = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
> +	bank->saved_polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
> +	if (bank->gpio_type == GPIO_TYPE_V2)
> +		bank->saved_bothedge = rockchip_gpio_readl(bank, bank->gpio_regs->int_bothedge);
>  	irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
>  }
>  
> @@ -496,7 +501,23 @@ static void rockchip_irq_resume(struct irq_data *d)
>  {
>  	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
>  	struct rockchip_pin_bank *bank = gc->private;
> +	u32 polarity = bank->saved_polarity;
> +
> +	/*
> +	 * Restore from hibernation follows a cold boot: write the enables and
> +	 * the trigger back before we unmask.
> +	 */
> +	if (bank->toggle_edge_mode) {
> +		u32 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
>  
> +		polarity &= ~bank->toggle_edge_mode;
> +		polarity |= ~data & bank->toggle_edge_mode;
> +	}
> +	rockchip_gpio_writel(bank, bank->saved_en, bank->gpio_regs->int_en);
> +	rockchip_gpio_writel(bank, bank->saved_type, bank->gpio_regs->int_type);
> +	rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);

[Severity: High]
Does recomputing polarity from ext_port here clear pending toggle_edge_mode
interrupts on GPIO_TYPE_V1 before rockchip_irq_demux() can handle them?

On GPIO_TYPE_V1, rockchip_irq_set_type() emulates IRQ_TYPE_EDGE_BOTH by
configuring a level-sensitive trigger in int_type and arming int_polarity to
the inverse of ext_port.  When the pin changes state, int_status remains
asserted only while int_polarity matches the new pin level, until
rockchip_irq_demux() flips int_polarity and dispatches the IRQ.

Because rockchip_irq_resume() runs via syscore_resume() while CPU interrupts
are still disabled, overwriting bank->saved_polarity with ~data when a pin
transitioned during suspend or hibernation flips int_polarity away from the
active level and drops the pending wakeup or edge event.  Restoring
bank->saved_polarity directly preserves the pending level condition for
rockchip_irq_demux() to flip and dispatch once interrupts are re-enabled.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261107-b4-gpio-rockchip-hib-v1-1-19f4d163a55e@iav.lv?part=1