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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b872152ee10sm534347566b.34.2026.01.13.07.31.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Jan 2026 07:32:01 -0800 (PST) Message-ID: <0f786783-db0d-4bae-b3ea-cab2ea85223e@oss.qualcomm.com> Date: Tue, 13 Jan 2026 16:31:58 +0100 Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/3] Retrieve information about DDR from SMEM To: Connor Abbott , Konrad Dybcio Cc: Bjorn Andersson , Kees Cook , "Gustavo A. R. Silva" , Rob Clark , Sean Paul , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org References: <20260108-topic-smem_dramc-v3-0-6b64df58a017@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: GpWhma3m-hzGzOzwepgQV-eHm8Q72ufz X-Proofpoint-GUID: GpWhma3m-hzGzOzwepgQV-eHm8Q72ufz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEzMDEyOSBTYWx0ZWRfX4l6123gg+fNI zLxvS0Bjhw8OCxPEilo5D3OvEh8NXWZqDyozmG7zy0406dyLrRUQBOx4yoz9GX4IPjWoPxi9TBU tPY0/NuBM5o/Hqyy/LtAvdn+BI7EnONnKQ7nl2yFeq8cgwLd6C9FIvATEUgrcToM+Y0AdtQPp51 GsShZzM1kKcpDNaDwyzpTnlCQQioa7sDQTNkR/Y37s7v8ZwhpjANvpO+KdKuMKZwoJzzaAa7pQF ZJCewOOXG5rvKhha8K/yxZ8IWvx3m+dqTCh6PErVC0hsBDZ+tSIbjVrS05ollA/5yf8fyd0MoTq sv4pYwOGwFErfqtx6VToWYWfz79LjTwNtQinET+c5Ltr+NLuRJmRwhbMtmuZytH7cg4kV5KPUM0 SIjLGZmao5roSlc2PgGhc/gz21CF1JKXklDgOurfsNIrukOJPqtPAToDs3xcxhx41qB0ZvuW1ST 5M4lMsOi7RF5p/1ZdYQ== X-Authority-Analysis: v=2.4 cv=PvSergM3 c=1 sm=1 tr=0 ts=69666576 cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=zvAHPaQ1O9Bprg_nwmMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-13_03,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601130129 On 1/9/26 8:11 PM, Connor Abbott wrote: > On Thu, Jan 8, 2026 at 9:22 AM Konrad Dybcio wrote: >> >> SMEM allows the OS to retrieve information about the DDR memory. >> Among that information, is a semi-magic value called 'HBB', or Highest >> Bank address Bit, which multimedia drivers (for hardware like Adreno >> and MDSS) must retrieve in order to program the IP blocks correctly. >> >> This series introduces an API to retrieve that value, uses it in the >> aforementioned programming sequences and exposes available DDR >> frequencies in debugfs (to e.g. pass to aoss_qmp debugfs). More >> information can be exposed in the future, as needed. >> >> Patch 3 should really be merged after 1&2 > > No. The HBB value currently returned by the bootloader is *not* always > the same as what we use currently, because some SoCs (like SM8250) > with the same DT ship with multiple different DRAM configurations and > we've been using a sub-optimal value the whole time. After all, that's > the whole point of using the bootloader value. But patches 1&2 will > only make the DPU use the bootloader value for HBB, not the GPU. So on > one of the affected SoCs, it will introduce a mismatch. You can't > change anything until the GPU side uses the new ubwc config as its > source of truth. You're right, sorry for that Konrad