[PATCH v5 0/4] Add support for QoS configuration

[PATCH v5 0/4] Add support for QoS configuration

[Odelu Kukatla]

This series adds QoS support for QNOC type device which can be found on
SC7280 platform. It adds support for programming priority,
priority forward disable and urgency forwarding. This helps in
priortizing the traffic originating from different interconnect masters
at NOC (Network On Chip).

Changes in v5:
 - Replaced platform_get_resource() and devm_ioremap_resource() with
   devm_platform_ioremap_resource() API.
 - Initialized the qosbox pointer in ICC node using compound literal.
 - Added conditional check for clock property in dt-bindings to the 
   providers which need clocks.

Odelu Kukatla (4):
  interconnect: qcom: icc-rpmh: Add QoS configuration support
  interconnect: qcom: sc7280: enable QoS configuration
  dt-bindings: interconnect: add clock property to enable QOS on SC7280
  arm64: dts: qcom: sc7280: Add clocks for QOS configuration

 .../interconnect/qcom,sc7280-rpmh.yaml        |  53 ++++
 arch/arm64/boot/dts/qcom/sc7280.dtsi          |   3 +
 drivers/interconnect/qcom/icc-rpmh.c          |  93 ++++++
 drivers/interconnect/qcom/icc-rpmh.h          |  35 +++
 drivers/interconnect/qcom/sc7280.c            | 274 ++++++++++++++++++
 5 files changed, 458 insertions(+)

-- 
2.17.1

[PATCH v5 1/4] interconnect: qcom: icc-rpmh: Add QoS configuration support

[Odelu Kukatla]

Add QoS support for QNOC device for configuring priority,
priority forward disable and urgency forwarding. QoS is required
to prioritize the traffic originating from different interconnect
masters at NoC (Network On Chip).

Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
---
 drivers/interconnect/qcom/icc-rpmh.c | 93 ++++++++++++++++++++++++++++
 drivers/interconnect/qcom/icc-rpmh.h | 35 +++++++++++
 2 files changed, 128 insertions(+)

diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
index c1aa265c1f4e..ceea9522df83 100644
--- a/drivers/interconnect/qcom/icc-rpmh.c
+++ b/drivers/interconnect/qcom/icc-rpmh.c
@@ -1,8 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <linux/bitfield.h>
+#include <linux/clk.h>
 #include <linux/interconnect.h>
 #include <linux/interconnect-provider.h>
 #include <linux/module.h>
@@ -14,6 +17,38 @@
 #include "icc-common.h"
 #include "icc-rpmh.h"
 
+/* QNOC QoS */
+#define QOSGEN_MAINCTL_LO(p, qp)	(0x8 + (p->port_offsets[qp]))
+#define QOS_SLV_URG_MSG_EN_MASK		GENMASK(3, 3)
+#define QOS_DFLT_PRIO_MASK		GENMASK(6, 4)
+#define QOS_DISABLE_MASK		GENMASK(24, 24)
+
+/**
+ * qcom_icc_set_qos - initialize static QoS configurations
+ * @qp: qcom icc provider to which @node belongs
+ * @node: qcom icc node to operate on
+ */
+static void qcom_icc_set_qos(struct qcom_icc_provider *qp,
+			     struct qcom_icc_node *node)
+{
+	const struct qcom_icc_qosbox *qos = node->qosbox;
+	int port;
+
+	for (port = 0; port < qos->num_ports; port++) {
+		regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
+				   QOS_DISABLE_MASK,
+				   FIELD_PREP(QOS_DISABLE_MASK, qos->prio_fwd_disable));
+
+		regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
+				   QOS_DFLT_PRIO_MASK,
+				   FIELD_PREP(QOS_DFLT_PRIO_MASK, qos->prio));
+
+		regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
+				   QOS_SLV_URG_MSG_EN_MASK,
+				   FIELD_PREP(QOS_SLV_URG_MSG_EN_MASK, qos->urg_fwd));
+	}
+}
+
 /**
  * qcom_icc_pre_aggregate - cleans up stale values from prior icc_set
  * @node: icc node to operate on
@@ -159,6 +194,36 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
 }
 EXPORT_SYMBOL_GPL(qcom_icc_bcm_init);
 
+/**
+ * qcom_icc_rpmh_configure_qos - configure QoS parameters
+ * @qp: qcom icc provider associated with QoS endpoint nodes
+ *
+ * Return: 0 on success, or an error code otherwise
+ */
+static int qcom_icc_rpmh_configure_qos(struct qcom_icc_provider *qp)
+{
+	struct qcom_icc_node *qnode;
+	size_t i;
+	int ret;
+
+	ret = clk_bulk_prepare_enable(qp->num_clks, qp->clks);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < qp->num_nodes; i++) {
+		qnode = qp->nodes[i];
+		if (!qnode)
+			continue;
+
+		if (qnode->qosbox)
+			qcom_icc_set_qos(qp, qnode);
+	}
+
+	clk_bulk_disable_unprepare(qp->num_clks, qp->clks);
+
+	return ret;
+}
+
 int qcom_icc_rpmh_probe(struct platform_device *pdev)
 {
 	const struct qcom_icc_desc *desc;
@@ -199,7 +264,9 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
 
 	qp->dev = dev;
 	qp->bcms = desc->bcms;
+	qp->nodes = desc->nodes;
 	qp->num_bcms = desc->num_bcms;
+	qp->num_nodes = desc->num_nodes;
 
 	qp->voter = of_bcm_voter_get(qp->dev, NULL);
 	if (IS_ERR(qp->voter))
@@ -229,6 +296,32 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
 		data->nodes[i] = node;
 	}
 
+	if (desc->config) {
+		struct resource *res;
+		void __iomem *base;
+
+		base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+		if (IS_ERR(base))
+			goto skip_qos_config;
+
+		qp->regmap = devm_regmap_init_mmio(dev, base, desc->config);
+		if (IS_ERR(qp->regmap)) {
+			dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap));
+			goto skip_qos_config;
+		}
+
+		qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);
+		if (qp->num_clks < 0) {
+			dev_info(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks);
+			goto skip_qos_config;
+		}
+
+		ret = qcom_icc_rpmh_configure_qos(qp);
+		if (ret)
+			dev_info(dev, "Failed to program QoS: %d\n", ret);
+	}
+
+skip_qos_config:
 	ret = icc_provider_register(provider);
 	if (ret)
 		goto err_remove_nodes;
diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
index 2de29460e808..9a5142c70486 100644
--- a/drivers/interconnect/qcom/icc-rpmh.h
+++ b/drivers/interconnect/qcom/icc-rpmh.h
@@ -1,12 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
 #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
 
 #include <dt-bindings/interconnect/qcom,icc.h>
+#include <linux/regmap.h>
 
 #define to_qcom_provider(_provider) \
 	container_of(_provider, struct qcom_icc_provider, provider)
@@ -18,6 +20,11 @@
  * @bcms: list of bcms that maps to the provider
  * @num_bcms: number of @bcms
  * @voter: bcm voter targeted by this provider
+ * @nodes: list of icc nodes that maps to the provider
+ * @num_nodes: number of @nodes
+ * @regmap: used for QoS, register access
+ * @clks : clks required for register access
+ * @num_clks: number of @clks
  */
 struct qcom_icc_provider {
 	struct icc_provider provider;
@@ -25,6 +32,11 @@ struct qcom_icc_provider {
 	struct qcom_icc_bcm * const *bcms;
 	size_t num_bcms;
 	struct bcm_voter *voter;
+	struct qcom_icc_node * const *nodes;
+	size_t num_nodes;
+	struct regmap *regmap;
+	struct clk_bulk_data *clks;
+	int num_clks;
 };
 
 /**
@@ -41,6 +53,26 @@ struct bcm_db {
 	u8 reserved;
 };
 
+#define MAX_PORTS		2
+
+/**
+ * struct qcom_icc_qosbox - Qualcomm specific QoS config
+ * @prio: priority value assigned to requests on the node
+ * @urg_fwd: whether to forward the urgency promotion issued by master
+ * (endpoint), or discard
+ * @prio_fwd_disable: whether to forward the priority driven by master, or
+ * override by @prio
+ * @num_ports: number of @ports
+ * @port_offsets: qos register offsets
+ */
+struct qcom_icc_qosbox {
+	const u32 prio;
+	const bool urg_fwd;
+	const bool prio_fwd_disable;
+	const u32 num_ports;
+	const u32 port_offsets[MAX_PORTS];
+};
+
 #define MAX_LINKS		128
 #define MAX_BCMS		64
 #define MAX_BCM_PER_NODE	3
@@ -58,6 +90,7 @@ struct bcm_db {
  * @max_peak: current max aggregate value of all peak bw requests
  * @bcms: list of bcms associated with this logical node
  * @num_bcms: num of @bcms
+ * @qosbox: QoS config data associated with node
  */
 struct qcom_icc_node {
 	const char *name;
@@ -70,6 +103,7 @@ struct qcom_icc_node {
 	u64 max_peak[QCOM_ICC_NUM_BUCKETS];
 	struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE];
 	size_t num_bcms;
+	const struct qcom_icc_qosbox *qosbox;
 };
 
 /**
@@ -114,6 +148,7 @@ struct qcom_icc_fabric {
 };
 
 struct qcom_icc_desc {
+	const struct regmap_config *config;
 	struct qcom_icc_node * const *nodes;
 	size_t num_nodes;
 	struct qcom_icc_bcm * const *bcms;
-- 
2.17.1

Re: [PATCH v5 1/4] interconnect: qcom: icc-rpmh: Add QoS configuration support

[Konrad Dybcio]

On 6/7/24 19:39, Odelu Kukatla wrote:
> Add QoS support for QNOC device for configuring priority,
> priority forward disable and urgency forwarding. QoS is required
> to prioritize the traffic originating from different interconnect
> masters at NoC (Network On Chip).
> 
> Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

[PATCH v5 2/4] interconnect: qcom: sc7280: enable QoS configuration

[Odelu Kukatla]

Enable QoS configuration for master ports with predefined values
for priority and urgency forawrding.

Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
---
 drivers/interconnect/qcom/sc7280.c | 274 +++++++++++++++++++++++++++++
 1 file changed, 274 insertions(+)

diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c
index 7d33694368e8..759c609a20bf 100644
--- a/drivers/interconnect/qcom/sc7280.c
+++ b/drivers/interconnect/qcom/sc7280.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  */
 
@@ -21,6 +22,12 @@ static struct qcom_icc_node qhm_qspi = {
 	.id = SC7280_MASTER_QSPI_0,
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x7000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A1NOC_SNOC },
 };
@@ -30,6 +37,12 @@ static struct qcom_icc_node qhm_qup0 = {
 	.id = SC7280_MASTER_QUP_0,
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x11000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A1NOC_SNOC },
 };
@@ -39,6 +52,12 @@ static struct qcom_icc_node qhm_qup1 = {
 	.id = SC7280_MASTER_QUP_1,
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x8000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A1NOC_SNOC },
 };
@@ -57,6 +76,12 @@ static struct qcom_icc_node xm_sdc1 = {
 	.id = SC7280_MASTER_SDCC_1,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xc000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A1NOC_SNOC },
 };
@@ -66,6 +91,12 @@ static struct qcom_icc_node xm_sdc2 = {
 	.id = SC7280_MASTER_SDCC_2,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xe000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A1NOC_SNOC },
 };
@@ -75,6 +106,12 @@ static struct qcom_icc_node xm_sdc4 = {
 	.id = SC7280_MASTER_SDCC_4,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x9000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A1NOC_SNOC },
 };
@@ -84,6 +121,12 @@ static struct qcom_icc_node xm_ufs_mem = {
 	.id = SC7280_MASTER_UFS_MEM,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xa000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A1NOC_SNOC },
 };
@@ -102,6 +145,12 @@ static struct qcom_icc_node xm_usb3_0 = {
 	.id = SC7280_MASTER_USB3_0,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xb000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A1NOC_SNOC },
 };
@@ -111,6 +160,12 @@ static struct qcom_icc_node qhm_qdss_bam = {
 	.id = SC7280_MASTER_QDSS_BAM,
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x18000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A2NOC_SNOC },
 };
@@ -129,6 +184,12 @@ static struct qcom_icc_node qnm_cnoc_datapath = {
 	.id = SC7280_MASTER_CNOC_A2NOC,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x1c000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A2NOC_SNOC },
 };
@@ -138,6 +199,12 @@ static struct qcom_icc_node qxm_crypto = {
 	.id = SC7280_MASTER_CRYPTO,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x1d000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A2NOC_SNOC },
 };
@@ -147,6 +214,12 @@ static struct qcom_icc_node qxm_ipa = {
 	.id = SC7280_MASTER_IPA,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x10000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A2NOC_SNOC },
 };
@@ -173,6 +246,12 @@ static struct qcom_icc_node xm_qdss_etr = {
 	.id = SC7280_MASTER_QDSS_ETR,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x15000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_A2NOC_SNOC },
 };
@@ -305,6 +384,12 @@ static struct qcom_icc_node alm_gpu_tcu = {
 	.id = SC7280_MASTER_GPU_TCU,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd7000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 2,
 	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
 };
@@ -314,6 +399,12 @@ static struct qcom_icc_node alm_sys_tcu = {
 	.id = SC7280_MASTER_SYS_TCU,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd6000 },
+		.prio = 6,
+		.urg_fwd = 0,
+	},
 	.num_links = 2,
 	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
 };
@@ -333,6 +424,12 @@ static struct qcom_icc_node qnm_cmpnoc = {
 	.id = SC7280_MASTER_COMPUTE_NOC,
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x21000, 0x61000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 2,
 	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
 };
@@ -353,6 +450,12 @@ static struct qcom_icc_node qnm_gpu = {
 	.id = SC7280_MASTER_GFX3D,
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x22000, 0x62000 },
+		.prio = 0,
+		.urg_fwd = 0,
+	},
 	.num_links = 2,
 	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
 };
@@ -362,6 +465,12 @@ static struct qcom_icc_node qnm_mnoc_hf = {
 	.id = SC7280_MASTER_MNOC_HF_MEM_NOC,
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x23000, 0x63000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_LLCC },
 };
@@ -371,6 +480,12 @@ static struct qcom_icc_node qnm_mnoc_sf = {
 	.id = SC7280_MASTER_MNOC_SF_MEM_NOC,
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xcf000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 2,
 	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
 };
@@ -389,6 +504,12 @@ static struct qcom_icc_node qnm_snoc_gc = {
 	.id = SC7280_MASTER_SNOC_GC_MEM_NOC,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd3000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_LLCC },
 };
@@ -398,6 +519,12 @@ static struct qcom_icc_node qnm_snoc_sf = {
 	.id = SC7280_MASTER_SNOC_SF_MEM_NOC,
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd4000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 3,
 	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
 		   SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
@@ -437,6 +564,12 @@ static struct qcom_icc_node qnm_video0 = {
 	.id = SC7280_MASTER_VIDEO_P0,
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x14000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
 };
@@ -446,6 +579,12 @@ static struct qcom_icc_node qnm_video_cpu = {
 	.id = SC7280_MASTER_VIDEO_PROC,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x15000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
 };
@@ -455,6 +594,12 @@ static struct qcom_icc_node qxm_camnoc_hf = {
 	.id = SC7280_MASTER_CAMNOC_HF,
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x10000, 0x10180 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
 };
@@ -464,6 +609,12 @@ static struct qcom_icc_node qxm_camnoc_icp = {
 	.id = SC7280_MASTER_CAMNOC_ICP,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x11000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
 };
@@ -473,6 +624,12 @@ static struct qcom_icc_node qxm_camnoc_sf = {
 	.id = SC7280_MASTER_CAMNOC_SF,
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x12000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
 };
@@ -482,6 +639,12 @@ static struct qcom_icc_node qxm_mdp0 = {
 	.id = SC7280_MASTER_MDP0,
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x16000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
 };
@@ -536,6 +699,12 @@ static struct qcom_icc_node qxm_pimem = {
 	.id = SC7280_MASTER_PIMEM,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x8000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
 };
@@ -545,6 +714,12 @@ static struct qcom_icc_node xm_gic = {
 	.id = SC7280_MASTER_GIC,
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xa000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
 };
@@ -1502,7 +1677,16 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
 	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
 };
 
+static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x1c080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_aggre1_noc = {
+	.config = &sc7280_aggre1_noc_regmap_config,
 	.nodes = aggre1_noc_nodes,
 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
 	.bcms = aggre1_noc_bcms,
@@ -1513,6 +1697,14 @@ static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
 	&bcm_ce0,
 };
 
+static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x2b080,
+	.fast_io = true,
+};
+
 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
 	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
 	[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
@@ -1525,6 +1717,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
 };
 
 static const struct qcom_icc_desc sc7280_aggre2_noc = {
+	.config = &sc7280_aggre2_noc_regmap_config,
 	.nodes = aggre2_noc_nodes,
 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
 	.bcms = aggre2_noc_bcms,
@@ -1605,7 +1798,16 @@ static struct qcom_icc_node * const cnoc2_nodes[] = {
 	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
 };
 
+static const struct regmap_config sc7280_cnoc2_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x1000,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_cnoc2 = {
+	.config = &sc7280_cnoc2_regmap_config,
 	.nodes = cnoc2_nodes,
 	.num_nodes = ARRAY_SIZE(cnoc2_nodes),
 	.bcms = cnoc2_bcms,
@@ -1637,7 +1839,16 @@ static struct qcom_icc_node * const cnoc3_nodes[] = {
 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
 };
 
+static const struct regmap_config sc7280_cnoc3_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x1000,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_cnoc3 = {
+	.config = &sc7280_cnoc3_regmap_config,
 	.nodes = cnoc3_nodes,
 	.num_nodes = ARRAY_SIZE(cnoc3_nodes),
 	.bcms = cnoc3_bcms,
@@ -1653,7 +1864,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
 	[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
 };
 
+static const struct regmap_config sc7280_dc_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x5080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_dc_noc = {
+	.config = &sc7280_dc_noc_regmap_config,
 	.nodes = dc_noc_nodes,
 	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
 	.bcms = dc_noc_bcms,
@@ -1689,7 +1909,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
 	[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
 };
 
+static const struct regmap_config sc7280_gem_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0xe2200,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_gem_noc = {
+	.config = &sc7280_gem_noc_regmap_config,
 	.nodes = gem_noc_nodes,
 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
 	.bcms = gem_noc_bcms,
@@ -1709,7 +1938,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
 	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
 };
 
+static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0xf080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
+	.config = &sc7280_lpass_ag_noc_regmap_config,
 	.nodes = lpass_ag_noc_nodes,
 	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
 	.bcms = lpass_ag_noc_bcms,
@@ -1726,7 +1964,16 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
 	[SLAVE_EBI1] = &ebi,
 };
 
+static const struct regmap_config sc7280_mc_virt_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x4,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_mc_virt = {
+	.config = &sc7280_mc_virt_regmap_config,
 	.nodes = mc_virt_nodes,
 	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
 	.bcms = mc_virt_bcms,
@@ -1753,7 +2000,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
 };
 
+static const struct regmap_config sc7280_mmss_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x1e080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_mmss_noc = {
+	.config = &sc7280_mmss_noc_regmap_config,
 	.nodes = mmss_noc_nodes,
 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
 	.bcms = mmss_noc_bcms,
@@ -1772,7 +2028,16 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
 	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
 };
 
+static const struct regmap_config sc7280_nsp_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x10000,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_nsp_noc = {
+	.config = &sc7280_nsp_noc_regmap_config,
 	.nodes = nsp_noc_nodes,
 	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
 	.bcms = nsp_noc_bcms,
@@ -1797,7 +2062,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
 	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
 };
 
+static const struct regmap_config sc7280_system_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x15480,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc sc7280_system_noc = {
+	.config = &sc7280_system_noc_regmap_config,
 	.nodes = system_noc_nodes,
 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
 	.bcms = system_noc_bcms,
-- 
2.17.1

Re: [PATCH v5 2/4] interconnect: qcom: sc7280: enable QoS configuration

[Konrad Dybcio]

On 6/7/24 19:39, Odelu Kukatla wrote:
> Enable QoS configuration for master ports with predefined values
> for priority and urgency forawrding.
> 
> Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
> ---

msm-5.4 also has a qhm_gic node with QoS offset 0x9000, is that of any
importance, or can we forget it exists?

LGTM otherwise:

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

Re: [PATCH v5 2/4] interconnect: qcom: sc7280: enable QoS configuration

[Odelu Kukatla]

On 6/18/2024 8:16 PM, Konrad Dybcio wrote:
> 
> 
> On 6/7/24 19:39, Odelu Kukatla wrote:
>> Enable QoS configuration for master ports with predefined values
>> for priority and urgency forawrding.
>>
>> Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
>> ---
> 
> msm-5.4 also has a qhm_gic node with QoS offset 0x9000, is that of any
> importance, or can we forget it exists?
> 

qhm_gic node QoS is not that important, it is fine.

> LGTM otherwise:
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> Konrad

Thanks for the review!

Regards,
Odelu

Re: [PATCH v5 2/4] interconnect: qcom: sc7280: enable QoS configuration

[Bjorn Andersson]

On Fri, Jun 07, 2024 at 11:09:25PM GMT, Odelu Kukatla wrote:
> Enable QoS configuration for master ports with predefined values
> for priority and urgency forawrding.
> 

This patch causes QCS6490 RB3Gen2 to hit a bus timeout and crash during
boot, unless the associated DeviceTree change (adding clocks) is
present.

The two patches are reaching linux-next, and hence mainline, through
different code paths we now have periods where rb3gen2 is not bootable.
But more importantly, devices with current .dtbs installed can not boot
the new kernel.


It is not acceptable to introduce non-backwards compatible changes in
drivers (unless there's extraordinary reasons to do so).

Regards,
Bjorn

> Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
> ---
>  drivers/interconnect/qcom/sc7280.c | 274 +++++++++++++++++++++++++++++
>  1 file changed, 274 insertions(+)
> 
> diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c
> index 7d33694368e8..759c609a20bf 100644
> --- a/drivers/interconnect/qcom/sc7280.c
> +++ b/drivers/interconnect/qcom/sc7280.c
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
>   * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>   *
>   */
>  
> @@ -21,6 +22,12 @@ static struct qcom_icc_node qhm_qspi = {
>  	.id = SC7280_MASTER_QSPI_0,
>  	.channels = 1,
>  	.buswidth = 4,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x7000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A1NOC_SNOC },
>  };
> @@ -30,6 +37,12 @@ static struct qcom_icc_node qhm_qup0 = {
>  	.id = SC7280_MASTER_QUP_0,
>  	.channels = 1,
>  	.buswidth = 4,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x11000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A1NOC_SNOC },
>  };
> @@ -39,6 +52,12 @@ static struct qcom_icc_node qhm_qup1 = {
>  	.id = SC7280_MASTER_QUP_1,
>  	.channels = 1,
>  	.buswidth = 4,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x8000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A1NOC_SNOC },
>  };
> @@ -57,6 +76,12 @@ static struct qcom_icc_node xm_sdc1 = {
>  	.id = SC7280_MASTER_SDCC_1,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xc000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A1NOC_SNOC },
>  };
> @@ -66,6 +91,12 @@ static struct qcom_icc_node xm_sdc2 = {
>  	.id = SC7280_MASTER_SDCC_2,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xe000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A1NOC_SNOC },
>  };
> @@ -75,6 +106,12 @@ static struct qcom_icc_node xm_sdc4 = {
>  	.id = SC7280_MASTER_SDCC_4,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x9000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A1NOC_SNOC },
>  };
> @@ -84,6 +121,12 @@ static struct qcom_icc_node xm_ufs_mem = {
>  	.id = SC7280_MASTER_UFS_MEM,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xa000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A1NOC_SNOC },
>  };
> @@ -102,6 +145,12 @@ static struct qcom_icc_node xm_usb3_0 = {
>  	.id = SC7280_MASTER_USB3_0,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xb000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A1NOC_SNOC },
>  };
> @@ -111,6 +160,12 @@ static struct qcom_icc_node qhm_qdss_bam = {
>  	.id = SC7280_MASTER_QDSS_BAM,
>  	.channels = 1,
>  	.buswidth = 4,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x18000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A2NOC_SNOC },
>  };
> @@ -129,6 +184,12 @@ static struct qcom_icc_node qnm_cnoc_datapath = {
>  	.id = SC7280_MASTER_CNOC_A2NOC,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x1c000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A2NOC_SNOC },
>  };
> @@ -138,6 +199,12 @@ static struct qcom_icc_node qxm_crypto = {
>  	.id = SC7280_MASTER_CRYPTO,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x1d000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A2NOC_SNOC },
>  };
> @@ -147,6 +214,12 @@ static struct qcom_icc_node qxm_ipa = {
>  	.id = SC7280_MASTER_IPA,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x10000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A2NOC_SNOC },
>  };
> @@ -173,6 +246,12 @@ static struct qcom_icc_node xm_qdss_etr = {
>  	.id = SC7280_MASTER_QDSS_ETR,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x15000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_A2NOC_SNOC },
>  };
> @@ -305,6 +384,12 @@ static struct qcom_icc_node alm_gpu_tcu = {
>  	.id = SC7280_MASTER_GPU_TCU,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xd7000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 2,
>  	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
>  };
> @@ -314,6 +399,12 @@ static struct qcom_icc_node alm_sys_tcu = {
>  	.id = SC7280_MASTER_SYS_TCU,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xd6000 },
> +		.prio = 6,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 2,
>  	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
>  };
> @@ -333,6 +424,12 @@ static struct qcom_icc_node qnm_cmpnoc = {
>  	.id = SC7280_MASTER_COMPUTE_NOC,
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x21000, 0x61000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 2,
>  	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
>  };
> @@ -353,6 +450,12 @@ static struct qcom_icc_node qnm_gpu = {
>  	.id = SC7280_MASTER_GFX3D,
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x22000, 0x62000 },
> +		.prio = 0,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 2,
>  	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
>  };
> @@ -362,6 +465,12 @@ static struct qcom_icc_node qnm_mnoc_hf = {
>  	.id = SC7280_MASTER_MNOC_HF_MEM_NOC,
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x23000, 0x63000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_LLCC },
>  };
> @@ -371,6 +480,12 @@ static struct qcom_icc_node qnm_mnoc_sf = {
>  	.id = SC7280_MASTER_MNOC_SF_MEM_NOC,
>  	.channels = 1,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xcf000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 2,
>  	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
>  };
> @@ -389,6 +504,12 @@ static struct qcom_icc_node qnm_snoc_gc = {
>  	.id = SC7280_MASTER_SNOC_GC_MEM_NOC,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xd3000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_LLCC },
>  };
> @@ -398,6 +519,12 @@ static struct qcom_icc_node qnm_snoc_sf = {
>  	.id = SC7280_MASTER_SNOC_SF_MEM_NOC,
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xd4000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 3,
>  	.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
>  		   SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
> @@ -437,6 +564,12 @@ static struct qcom_icc_node qnm_video0 = {
>  	.id = SC7280_MASTER_VIDEO_P0,
>  	.channels = 1,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x14000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
>  };
> @@ -446,6 +579,12 @@ static struct qcom_icc_node qnm_video_cpu = {
>  	.id = SC7280_MASTER_VIDEO_PROC,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x15000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
>  };
> @@ -455,6 +594,12 @@ static struct qcom_icc_node qxm_camnoc_hf = {
>  	.id = SC7280_MASTER_CAMNOC_HF,
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x10000, 0x10180 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
>  };
> @@ -464,6 +609,12 @@ static struct qcom_icc_node qxm_camnoc_icp = {
>  	.id = SC7280_MASTER_CAMNOC_ICP,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x11000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
>  };
> @@ -473,6 +624,12 @@ static struct qcom_icc_node qxm_camnoc_sf = {
>  	.id = SC7280_MASTER_CAMNOC_SF,
>  	.channels = 1,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x12000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
>  };
> @@ -482,6 +639,12 @@ static struct qcom_icc_node qxm_mdp0 = {
>  	.id = SC7280_MASTER_MDP0,
>  	.channels = 1,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x16000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
>  };
> @@ -536,6 +699,12 @@ static struct qcom_icc_node qxm_pimem = {
>  	.id = SC7280_MASTER_PIMEM,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x8000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
>  };
> @@ -545,6 +714,12 @@ static struct qcom_icc_node xm_gic = {
>  	.id = SC7280_MASTER_GIC,
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xa000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +	},
>  	.num_links = 1,
>  	.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
>  };
> @@ -1502,7 +1677,16 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
>  	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
>  };
>  
> +static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x1c080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_aggre1_noc = {
> +	.config = &sc7280_aggre1_noc_regmap_config,
>  	.nodes = aggre1_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
>  	.bcms = aggre1_noc_bcms,
> @@ -1513,6 +1697,14 @@ static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
>  	&bcm_ce0,
>  };
>  
> +static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x2b080,
> +	.fast_io = true,
> +};
> +
>  static struct qcom_icc_node * const aggre2_noc_nodes[] = {
>  	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
>  	[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
> @@ -1525,6 +1717,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
>  };
>  
>  static const struct qcom_icc_desc sc7280_aggre2_noc = {
> +	.config = &sc7280_aggre2_noc_regmap_config,
>  	.nodes = aggre2_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
>  	.bcms = aggre2_noc_bcms,
> @@ -1605,7 +1798,16 @@ static struct qcom_icc_node * const cnoc2_nodes[] = {
>  	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
>  };
>  
> +static const struct regmap_config sc7280_cnoc2_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x1000,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_cnoc2 = {
> +	.config = &sc7280_cnoc2_regmap_config,
>  	.nodes = cnoc2_nodes,
>  	.num_nodes = ARRAY_SIZE(cnoc2_nodes),
>  	.bcms = cnoc2_bcms,
> @@ -1637,7 +1839,16 @@ static struct qcom_icc_node * const cnoc3_nodes[] = {
>  	[SLAVE_TCU] = &xs_sys_tcu_cfg,
>  };
>  
> +static const struct regmap_config sc7280_cnoc3_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x1000,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_cnoc3 = {
> +	.config = &sc7280_cnoc3_regmap_config,
>  	.nodes = cnoc3_nodes,
>  	.num_nodes = ARRAY_SIZE(cnoc3_nodes),
>  	.bcms = cnoc3_bcms,
> @@ -1653,7 +1864,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
>  	[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
>  };
>  
> +static const struct regmap_config sc7280_dc_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x5080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_dc_noc = {
> +	.config = &sc7280_dc_noc_regmap_config,
>  	.nodes = dc_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
>  	.bcms = dc_noc_bcms,
> @@ -1689,7 +1909,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
>  	[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
>  };
>  
> +static const struct regmap_config sc7280_gem_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0xe2200,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_gem_noc = {
> +	.config = &sc7280_gem_noc_regmap_config,
>  	.nodes = gem_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
>  	.bcms = gem_noc_bcms,
> @@ -1709,7 +1938,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
>  	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
>  };
>  
> +static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0xf080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
> +	.config = &sc7280_lpass_ag_noc_regmap_config,
>  	.nodes = lpass_ag_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
>  	.bcms = lpass_ag_noc_bcms,
> @@ -1726,7 +1964,16 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
>  	[SLAVE_EBI1] = &ebi,
>  };
>  
> +static const struct regmap_config sc7280_mc_virt_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x4,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_mc_virt = {
> +	.config = &sc7280_mc_virt_regmap_config,
>  	.nodes = mc_virt_nodes,
>  	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
>  	.bcms = mc_virt_bcms,
> @@ -1753,7 +2000,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
>  	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
>  };
>  
> +static const struct regmap_config sc7280_mmss_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x1e080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_mmss_noc = {
> +	.config = &sc7280_mmss_noc_regmap_config,
>  	.nodes = mmss_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
>  	.bcms = mmss_noc_bcms,
> @@ -1772,7 +2028,16 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
>  	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
>  };
>  
> +static const struct regmap_config sc7280_nsp_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x10000,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_nsp_noc = {
> +	.config = &sc7280_nsp_noc_regmap_config,
>  	.nodes = nsp_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
>  	.bcms = nsp_noc_bcms,
> @@ -1797,7 +2062,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
>  	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
>  };
>  
> +static const struct regmap_config sc7280_system_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x15480,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc sc7280_system_noc = {
> +	.config = &sc7280_system_noc_regmap_config,
>  	.nodes = system_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(system_noc_nodes),
>  	.bcms = system_noc_bcms,
> -- 
> 2.17.1
> 

Re: [PATCH v5 2/4] interconnect: qcom: sc7280: enable QoS configuration

[Georgi Djakov]

On 1.07.24 19:42, Bjorn Andersson wrote:
> On Fri, Jun 07, 2024 at 11:09:25PM GMT, Odelu Kukatla wrote:
>> Enable QoS configuration for master ports with predefined values
>> for priority and urgency forawrding.
>>
> 
> This patch causes QCS6490 RB3Gen2 to hit a bus timeout and crash during
> boot, unless the associated DeviceTree change (adding clocks) is
> present.
> 
> The two patches are reaching linux-next, and hence mainline, through
> different code paths we now have periods where rb3gen2 is not bootable.
> But more importantly, devices with current .dtbs installed can not boot
> the new kernel.
> 
> 
> It is not acceptable to introduce non-backwards compatible changes in
> drivers (unless there's extraordinary reasons to do so).
> 

Thanks for the report, Bjorn! The intent of the patches is to keep it
backwards compatible. I think that the patch below should fix it.
I'll try to validate it and get it merged.

BR,
Georgi

-->8--
diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
index 93047defd5e2..487e562dbd22 100644
--- a/drivers/interconnect/qcom/icc-rpmh.c
+++ b/drivers/interconnect/qcom/icc-rpmh.c
@@ -311,7 +311,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
  		}

  		qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);
-		if (qp->num_clks < 0) {
+		if (qp->num_clks <= 0) {
  			dev_info(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks);
  			goto skip_qos_config;
  		}

Re: [PATCH v5 2/4] interconnect: qcom: sc7280: enable QoS configuration

[Odelu Kukatla]

On 7/2/2024 5:02 AM, Georgi Djakov wrote:
> On 1.07.24 19:42, Bjorn Andersson wrote:
>> On Fri, Jun 07, 2024 at 11:09:25PM GMT, Odelu Kukatla wrote:
>>> Enable QoS configuration for master ports with predefined values
>>> for priority and urgency forawrding.
>>>
>>
>> This patch causes QCS6490 RB3Gen2 to hit a bus timeout and crash during
>> boot, unless the associated DeviceTree change (adding clocks) is
>> present.
>>
>> The two patches are reaching linux-next, and hence mainline, through
>> different code paths we now have periods where rb3gen2 is not bootable.
>> But more importantly, devices with current .dtbs installed can not boot
>> the new kernel.
>>
>>
>> It is not acceptable to introduce non-backwards compatible changes in
>> drivers (unless there's extraordinary reasons to do so).
>>
> 
> Thanks for the report, Bjorn! The intent of the patches is to keep it
> backwards compatible. I think that the patch below should fix it.
> I'll try to validate it and get it merged.
> 
> BR,
> Georgi
> 

Thanks Bjorn and Georgi!
I will send a patch to address the boot up issue on old devices and keep it backwards compatible.

> -->8--
> diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
> index 93047defd5e2..487e562dbd22 100644
> --- a/drivers/interconnect/qcom/icc-rpmh.c
> +++ b/drivers/interconnect/qcom/icc-rpmh.c
> @@ -311,7 +311,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
>   		}
> 
>   		qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);
> -		if (qp->num_clks < 0) {
> +		if (qp->num_clks <= 0) {
>   			dev_info(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks);
>   			goto skip_qos_config;
>   		}
This will skip the QOS configuration for the providers which don't need any clock to be enabled.
we may have to add a flag at provider level to check if it is associated with qos clocks.


Thanks,
Odelu

[PATCH v5 3/4] dt-bindings: interconnect: add clock property to enable QOS on SC7280

[Odelu Kukatla]

Add clock property to enable the clocks required for accessing
QoS configuration registers.

Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
---
 .../interconnect/qcom,sc7280-rpmh.yaml        | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
index b135597d9489..9fce7203bd42 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
@@ -35,6 +35,10 @@ properties:
   reg:
     maxItems: 1
 
+  clocks:
+    minItems: 1
+    maxItems: 2
+
 required:
   - compatible
 
@@ -53,10 +57,50 @@ allOf:
       required:
         - reg
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc7280-aggre1-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre UFS PHY AXI clock
+            - description: aggre USB3 PRIM AXI clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc7280-aggre2-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: RPMH CC IPA clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc7280-aggre1-noc
+              - qcom,sc7280-aggre2-noc
+    then:
+      required:
+        - clocks
+    else:
+      properties:
+        clocks: false
+
 unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
     interconnect {
         compatible = "qcom,sc7280-clk-virt";
         #interconnect-cells = <2>;
@@ -69,3 +113,12 @@ examples:
         #interconnect-cells = <2>;
         qcom,bcm-voters = <&apps_bcm_voter>;
     };
+
+    interconnect@16e0000 {
+        reg = <0x016e0000 0x1c080>;
+        compatible = "qcom,sc7280-aggre1-noc";
+        #interconnect-cells = <2>;
+        qcom,bcm-voters = <&apps_bcm_voter>;
+        clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+    };
-- 
2.17.1

Re: [PATCH v5 3/4] dt-bindings: interconnect: add clock property to enable QOS on SC7280

[Rob Herring (Arm)]

On Fri, 07 Jun 2024 23:09:26 +0530, Odelu Kukatla wrote:
> Add clock property to enable the clocks required for accessing
> QoS configuration registers.
> 
> Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
> ---
>  .../interconnect/qcom,sc7280-rpmh.yaml        | 53 +++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v5 4/4] arm64: dts: qcom: sc7280: Add clocks for QOS configuration

[Odelu Kukatla]

Add clocks which need to be enbaled for configuring
QoS on sc7280.

Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ba43fba2c551..a3c640d394e9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2130,6 +2130,8 @@
 			reg = <0 0x016e0000 0 0x1c080>;
 			#interconnect-cells = <2>;
 			qcom,bcm-voters = <&apps_bcm_voter>;
+			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
 		};
 
 		aggre2_noc: interconnect@1700000 {
@@ -2137,6 +2139,7 @@
 			compatible = "qcom,sc7280-aggre2-noc";
 			#interconnect-cells = <2>;
 			qcom,bcm-voters = <&apps_bcm_voter>;
+			clocks = <&rpmhcc RPMH_IPA_CLK>;
 		};
 
 		mmss_noc: interconnect@1740000 {
-- 
2.17.1

Re: [PATCH v5 4/4] arm64: dts: qcom: sc7280: Add clocks for QOS configuration

[Konrad Dybcio]

On 6/7/24 19:39, Odelu Kukatla wrote:
> Add clocks which need to be enbaled for configuring
> QoS on sc7280.
> 
> Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

Re: [PATCH v5 4/4] arm64: dts: qcom: sc7280: Add clocks for QOS configuration

[Georgi Djakov]

On 7.06.24 20:39, Odelu Kukatla wrote:
> Add clocks which need to be enbaled for configuring
> QoS on sc7280.
> 

Nit: s/enbaled/enabled/

> Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>

In any case:
Acked-by: Georgi Djakov <djakov@kernel.org>

Bjorn, the dt-binding change is available in my icc-rpmh-qos branch
in case you want to make the dtbs checker happy when you apply this.

BR,
Georgi

> ---
>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index ba43fba2c551..a3c640d394e9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2130,6 +2130,8 @@
>   			reg = <0 0x016e0000 0 0x1c080>;
>   			#interconnect-cells = <2>;
>   			qcom,bcm-voters = <&apps_bcm_voter>;
> +			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> +				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
>   		};
>   
>   		aggre2_noc: interconnect@1700000 {
> @@ -2137,6 +2139,7 @@
>   			compatible = "qcom,sc7280-aggre2-noc";
>   			#interconnect-cells = <2>;
>   			qcom,bcm-voters = <&apps_bcm_voter>;
> +			clocks = <&rpmhcc RPMH_IPA_CLK>;
>   		};
>   
>   		mmss_noc: interconnect@1740000 {

Re: [PATCH v5 0/4] Add support for QoS configuration

[Dmitry Baryshkov]

On Fri, Jun 07, 2024 at 11:09:23PM +0530, Odelu Kukatla wrote:
> This series adds QoS support for QNOC type device which can be found on
> SC7280 platform. It adds support for programming priority,
> priority forward disable and urgency forwarding. This helps in
> priortizing the traffic originating from different interconnect masters
> at NOC (Network On Chip).
> 
> Changes in v5:
>  - Replaced platform_get_resource() and devm_ioremap_resource() with
>    devm_platform_ioremap_resource() API.
>  - Initialized the qosbox pointer in ICC node using compound literal.
>  - Added conditional check for clock property in dt-bindings to the 
>    providers which need clocks.

Please don't trim changelog from the previous revisions.

> 
> Odelu Kukatla (4):
>   interconnect: qcom: icc-rpmh: Add QoS configuration support
>   interconnect: qcom: sc7280: enable QoS configuration
>   dt-bindings: interconnect: add clock property to enable QOS on SC7280
>   arm64: dts: qcom: sc7280: Add clocks for QOS configuration
> 
>  .../interconnect/qcom,sc7280-rpmh.yaml        |  53 ++++
>  arch/arm64/boot/dts/qcom/sc7280.dtsi          |   3 +
>  drivers/interconnect/qcom/icc-rpmh.c          |  93 ++++++
>  drivers/interconnect/qcom/icc-rpmh.h          |  35 +++
>  drivers/interconnect/qcom/sc7280.c            | 274 ++++++++++++++++++
>  5 files changed, 458 insertions(+)
> 
> -- 
> 2.17.1
> 

-- 
With best wishes
Dmitry

Re: (subset) [PATCH v5 0/4] Add support for QoS configuration

[Bjorn Andersson]

On Fri, 07 Jun 2024 23:09:23 +0530, Odelu Kukatla wrote:
> This series adds QoS support for QNOC type device which can be found on
> SC7280 platform. It adds support for programming priority,
> priority forward disable and urgency forwarding. This helps in
> priortizing the traffic originating from different interconnect masters
> at NOC (Network On Chip).
> 
> Changes in v5:
>  - Replaced platform_get_resource() and devm_ioremap_resource() with
>    devm_platform_ioremap_resource() API.
>  - Initialized the qosbox pointer in ICC node using compound literal.
>  - Added conditional check for clock property in dt-bindings to the
>    providers which need clocks.
> 
> [...]

Applied, thanks!

[4/4] arm64: dts: qcom: sc7280: Add clocks for QOS configuration
      commit: 2b5004956affaa6dd1d23d431876ad533f10418b

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>