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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fe5bae43dsm45721935e9.5.2026.09.24.00.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 00:30:02 -0700 (PDT) From: Jerome Brunet To: Alex Elder , Brian Masney Cc: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, p.zabel@pengutronix.de, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/4] clk: toshiba: introduce a TC9564 SoC clock and reset driver In-Reply-To: <7147ce22-fc6d-4cff-9470-98e341da0a87@riscstar.com> References: <20260918165234.687224-1-elder@riscstar.com> <20260918165234.687224-4-elder@riscstar.com> <0785235b-de06-44d4-9068-ec706eeba848@riscstar.com> <1jcxu3adn6.fsf@starbuckisacylon.baylibre.com> <7147ce22-fc6d-4cff-9470-98e341da0a87@riscstar.com> Date: Thu, 24 Sep 2026 09:29:56 +0200 Message-ID: <1ja4p79kej.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On mer. 23 sept. 2026 at 16:33, Alex Elder wrote: > On 9/23/26 3:58 PM, Jerome Brunet wrote: >>>>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig >>>>> index f9592fd9ec2bb..50efa10d48450 100644 >>>>> --- a/drivers/clk/Kconfig >>>>> +++ b/drivers/clk/Kconfig >>>>> @@ -292,6 +292,17 @@ config COMMON_CLK_S2MPS11 >>>>> clock. These multi-function devices have two (S2MPS14) or three >>>>> (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. >>>>> >>>>> +config COMMON_CLK_TC9564 >>>>> + tristate "Toshiba TC9564 clock support" >>>>> + depends on TC9564_PCI >>>> select RESET_CONTROLLER >>> Thank you. The reset and clock drivers were previously separate >>> and the reset only became available if RESET_CONTROLLER was enabled. >>> Combining them means I need this. I will add it. >> Why did you combine them ? >> >> it would be a lot better if the reset were handled in >> drivers/reset rather than in clock. There has already been some work to >> move reset from clock back to reset. This often involve auxiliary drivers. > To be honest, I got a suggestion from someone to combine them, but > I said "no, I got feedback last year that separating them was > better." But then a second person told me that these are often > combined, so I took that as "two against one" and decided to > merge them. > > The other reason is that four registers are used: > #define CLK_CTRL0_OFFSET 0x1004 > #define RST_CTRL0_OFFSET 0x1008 > #define CLK_CTRL1_OFFSET 0x100c > define RST_CTRL1_OFFSET 0x1010 > > They alternate between clock and reset. The previous separated > drivers specified the two offsets for each driver in the reg > property. But somehow these interleaved registers seemed a > little off, so I thought the combined driver cleaned that up > a little. > > I don't have any strong preference one way or another. If you > think they're better separate, I don't mind separating them > again. The two drivers are extremely simple. Yes, SoC manufacturer tend to mix the 2, it is fairly usual and we used to have many drivers in clock providing reset too. We have been slowly cleaning that up over the past few years. To be clear it is not strictly forbbiden to mix ressources but putting things where they belong help review and maintainance. There are several examples you can look at with auxiliary device support, ./tenstorrent/atlantis-prcm.c is a good example. > > -Alex -- Jerome