From: Amelie Delaunay <amelie.delaunay@foss.st.com>
To: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Cc: <alexandre.torgue@foss.st.com>, <conor+dt@kernel.org>,
<devicetree@vger.kernel.org>, <dmaengine@vger.kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-hardening@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<mcoquelin.stm32@gmail.com>, <robh+dt@kernel.org>,
<vkoul@kernel.org>
Subject: Re: [PATCH 05/12] dmaengine: Add STM32 DMA3 support
Date: Tue, 7 May 2024 14:37:37 +0200 [thread overview]
Message-ID: <41d66c51-be2d-43a5-9dfd-9e94304980dd@foss.st.com> (raw)
In-Reply-To: <38193848-597d-47c1-9aea-5357e58f9983@wanadoo.fr>
Hi Christophe,
Thanks for the review.
On 5/4/24 16:27, Christophe JAILLET wrote:
> Le 23/04/2024 à 14:32, Amelie Delaunay a écrit :
>> STM32 DMA3 driver supports the 3 hardware configurations of the STM32
>> DMA3
>> controller:
>> - LPDMA (Low Power): 4 channels, no FIFO
>> - GPDMA (General Purpose): 16 channels, FIFO from 8 to 32 bytes
>> - HPDMA (High Performance): 16 channels, FIFO from 8 to 256 bytes
>> Hardware configuration of the channels is retrieved from the hardware
>> configuration registers.
>> The client can specify its channel requirements through device tree.
>> STM32 DMA3 channels can be individually reserved either because they are
>> secure, or dedicated to another CPU.
>> Indeed, channels availability depends on Resource Isolation Framework
>> (RIF) configuration. RIF grants access to buses with Compartiment ID
>> (CIF) filtering, secure and privilege level. It also assigns DMA channels
>> to one or several processors.
>> DMA channels used by Linux should be CID-filtered and statically assigned
>> to CID1 or shared with other CPUs but using semaphore. In case CID
>> filtering is not configured, dma-channel-mask property can be used to
>> specify available DMA channels to the kernel, otherwise such channels
>> will be marked as reserved and can't be used by Linux.
>>
>> Signed-off-by: Amelie Delaunay
>> <amelie.delaunay-rj0Iel/JR4NBDgjK7y7TUQ@public.gmane.org>
>> ---
>
> ...
>
>> + pm_runtime_set_active(&pdev->dev);
>> + pm_runtime_enable(&pdev->dev);
>> + pm_runtime_get_noresume(&pdev->dev);
>> + pm_runtime_put(&pdev->dev);
>> +
>> + dev_info(&pdev->dev, "STM32 DMA3 registered rev:%lu.%lu\n",
>> + FIELD_GET(VERR_MAJREV, verr), FIELD_GET(VERR_MINREV, verr));
>> +
>> + return 0;
>> +
>> +err_clk_disable:
>> + clk_disable_unprepare(ddata->clk);
>> +
>> + return ret;
>> +}
>> +
>> +static void stm32_dma3_remove(struct platform_device *pdev)
>> +{
>> + pm_runtime_disable(&pdev->dev);
>
> Hi,
>
> missing clk_disable_unprepare(ddata->clk);?
>
> as in the error handling path on the probe just above?
>
> CJ
>
Clock is entirely managed by pm_runtime, except in error path of probe
since pm_runtime is enabled only at the very end.
Clock is enabled with pm_runtime_resume_and_get() when a channel is
requested or when an asynchronous register access occurs (filter_fn,
debugfs, runtime_resume) and clock is disabled with
pm_runtime_put_sync() when releasing a channel or at the end of
asynchronous register access (filter_fn, debugfs, runtime_suspend).
Adding clk_disable_unprepare(ddata->clk); here leads to clock already
disabled/unprepared warnings in drivers/clk/clk.c
clk_core_disable()/clk_core_unprepare().
>> +}
>
> ...
>
Regards,
Amelie
next prev parent reply other threads:[~2024-05-07 12:39 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-23 12:32 [PATCH 00/12] Introduce STM32 DMA3 support Amelie Delaunay
2024-04-23 12:32 ` [PATCH 01/12] dt-bindings: dma: New directory for STM32 DMA controllers bindings Amelie Delaunay
2024-04-23 13:50 ` Rob Herring
2024-04-23 14:46 ` Amelie Delaunay
2024-04-23 12:32 ` [PATCH 02/12] dmaengine: stm32: New directory for STM32 DMA controllers drivers Amelie Delaunay
2024-04-23 12:32 ` [PATCH 03/12] MAINTAINERS: Add entry for STM32 DMA controllers drivers and documentation Amelie Delaunay
2024-04-23 12:32 ` [PATCH 04/12] dt-bindings: dma: Document STM32 DMA3 controller bindings Amelie Delaunay
2024-04-23 15:22 ` Rob Herring
2024-04-23 12:32 ` [PATCH 05/12] dmaengine: Add STM32 DMA3 support Amelie Delaunay
2024-05-04 12:40 ` Vinod Koul
2024-05-07 11:33 ` Amelie Delaunay
2024-05-07 20:26 ` Frank Li
2024-05-13 9:21 ` Amelie Delaunay
2024-05-15 18:45 ` Frank Li
2024-05-16 9:42 ` Amelie Delaunay
2024-05-04 14:27 ` Christophe JAILLET
2024-05-07 12:37 ` Amelie Delaunay [this message]
2024-05-15 18:56 ` Frank Li
2024-05-16 15:25 ` Amelie Delaunay
2024-05-16 17:09 ` Frank Li
2024-05-17 9:42 ` Amelie Delaunay
2024-05-17 14:57 ` Frank Li
2024-05-20 15:42 ` Amelie Delaunay
2024-04-23 12:32 ` [PATCH 06/12] dmaengine: stm32-dma3: add DMA_CYCLIC capability Amelie Delaunay
2024-04-23 12:32 ` [PATCH 07/12] dmaengine: stm32-dma3: add DMA_MEMCPY capability Amelie Delaunay
2024-04-23 12:32 ` [PATCH 08/12] dmaengine: stm32-dma3: add device_pause and device_resume ops Amelie Delaunay
2024-04-23 12:32 ` [PATCH 09/12] dmaengine: stm32-dma3: improve residue granularity Amelie Delaunay
2024-04-23 12:33 ` [PATCH 10/12] dmaengine: add channel device name to channel registration Amelie Delaunay
2024-04-23 12:33 ` [PATCH 11/12] dmaengine: stm32-dma3: defer channel registration to specify channel name Amelie Delaunay
2024-04-23 12:33 ` [PATCH 12/12] arm64: dts: st: add HPDMA nodes on stm32mp251 Amelie Delaunay
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