From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A754D1EB9F7; Fri, 21 Mar 2025 07:44:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742543072; cv=none; b=hYzIAslPk58VQhIa9tp05H+zjtMDcKTVvvfsQM1leohhiCH7tH9M7tcnt3GbGgHMDmyqb698J1zaLkbgp+6JRpISp8jjRx7fzPG842VH7VhzW6TcaJ095S4v/plNeegicKZh2hzYKFveE9Z9q1rMCY7xLLffj/kCoxO+7Shyzjo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742543072; c=relaxed/simple; bh=/YmjxGbakqtnak0HA4K/vKGsWFbKueiINUncr9XTSzw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=oBmYvLDytX3zsPntGOUXY/ZHD6Xlx90qbjJ5x73vAJX0QFSGqdN1zTiOlPKHvR8ajI4nz6KuV7P+pfYZBC1N+h+sqcH0DssGW/iKtTsz9IHbbo6qdNYXiF+NXzpAsXaqvDJuzH6zhMX074rAib7VqqvT150K8BKcwEeVbpqHdeY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uxtOttO2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uxtOttO2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9DE8C4CEE3; Fri, 21 Mar 2025 07:44:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742543072; bh=/YmjxGbakqtnak0HA4K/vKGsWFbKueiINUncr9XTSzw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=uxtOttO2F7v89LlJgh70CQiu5tLI6RaIemI9Z0u8HLRIqerUioGSSYZrDpkcA3sPv /3KXrgvNsfcYBjgOdatbfruVTVSwl1+thHkX/4svLdGjdAGPxr1R56cev/osRg9N+E XQOySpa5W7nDLmt3gtA6T85KBMttBU4UT2JX4NAwoUC2ZjQH/NEstb50hKeD5MTUe+ o2/4Y4f8v+vaGHApik+dNWVxLFpmvynZOa2PbQRTfGBGihAx3Hj69aLPViPfRYMQh+ ZzfXaT758lgC2uoV+MGwjGcfQoysEVl+q9Cn33/sVgS8DSNBPQrpI+MCfoi87U9CqV busQicYEiHfTA== Message-ID: <5127f2e7-cb38-4103-8799-551fdedd8152@kernel.org> Date: Fri, 21 Mar 2025 08:44:21 +0100 Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC To: Willie Thai , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, andrew@codeconstruct.com.au, kees@kernel.org, tony.luck@intel.com, gpiccoli@igalia.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, openbmc@lists.ozlabs.org Cc: leohu@nvidia.com, tingkaic@nvidia.com, dkodihalli@nvidia.com, Mars Yang , Andrew Lunn , Paul Menzel References: <20250320164633.101331-1-wthai@nvidia.com> <20250320164633.101331-2-wthai@nvidia.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 20/03/2025 17:46, Willie Thai wrote: > + > + leds { > + compatible = "gpio-leds"; > + led-0 { > + label = "uid_led"; > + gpios = <&sgpiom0 27 GPIO_ACTIVE_LOW>; > + }; > + led-1 { > + label = "fault_led"; > + gpios = <&sgpiom0 29 GPIO_ACTIVE_LOW>; > + }; > + led-2 { > + label = "power_led"; > + gpios = <&sgpiom0 31 GPIO_ACTIVE_LOW>; > + }; > + You still have stray blank lines in few places. > + }; > + > + buttons { > + button-power { > + label = "power-btn"; > + gpio = <&sgpiom0 156 GPIO_ACTIVE_LOW>; > + }; > + button-uid { > + label = "uid-btn"; > + gpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>; > + }; > + }; > + > +}; > + ... > +/* > + * Enable USB port A as device (via the virtual hub) to host > + */ > +&vhub { > + status = "okay"; > + pinctrl-names = "default"; > + /* > + * Uncomment below line to enable internal EHCI controller > + * Current config uses xHCI Port1 > + */ Comment makes no sense. > +}; > + > +&video { > + status = "okay"; > + memory-region = <&video_engine_memory>; > +}; > + ... > +&gpio0 { > + gpio-line-names = > + /*A0-A7*/ "", "", "", "", "", "", "", "", > + /*B0-B7*/ "", "", "", "", "", "", "", "", > + /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "", > + /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "", > + /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_SEL-O", > + "", "", "", "SGPIO_BMC_EN-O", > + /*F0-F7*/ "", "", "", "", "", "", "", "", > + /*G0-G7*/ "", "", "", "", "", "", "", "", > + /*H0-H7*/ "", "", "", "", "", "", "", "", > + /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_DDR4_TEN-O", > + /*J0-J7*/ "", "", "", "", "", "", "", "", > + /*K0-K7*/ "", "", "", "", "", "", "", "", > + /*L0-L7*/ "", "", "", "", "", "", "", "", > + /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "HMC_RESET_L-O", "STBY_POWER_EN-O", > + "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", > + /*N0-N7*/ "", "", "", "", "", "", "", "", > + /*O0-O7*/ "", "", "", "", "", "", "", "", > + /*P0-P7*/ "", "", "", "", "", "", "", "", > + /*Q0-Q7*/ "", "", "", "", "", "", "", "", > + /*R0-R7*/ "", "", "", "", "", "", "", "", > + /*S0-S7*/ "", "", "", "", "", "", "", "", > + /*T0-T7*/ "", "", "", "", "", "", "", "", > + /*U0-U7*/ "", "", "", "", "", "", "", "", > + /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "","", "", > + /*W0-W7*/ "", "", "", "", "", "", "", "", > + /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "", > + /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "", > + /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", ""; > +}; > + > +&gpio1 { > + /* 36 1.8V GPIOs */ > + gpio-line-names = > + /*A0-A7*/ "", "", "", "", "", "", "", "", > + /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","", > + /*C0-C7*/ "", "", "", "", "", "", "", "", > + /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_INT_L-I", > + /*E0-E7*/ "", "", "", "", "", "", "", ""; > +}; > + > +// EMMC group that excludes WP pin > +&pinctrl { > + pinctrl_emmcg5_default: emmcg5_default { No underscores in node names. > + function = "EMMC"; > + groups = "EMMCG5"; > + }; > +}; Best regards, Krzysztof