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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba455926c61sm1100136866b.63.2026.04.27.07.04.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Apr 2026 07:04:52 -0700 (PDT) Message-ID: Date: Mon, 27 Apr 2026 16:04:49 +0200 Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/14] media: qcom: camss: Add PM clock support and integrate with runtime PM To: Loic Poulain , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Kees Cook , "Gustavo A. R. Silva" , Bryan O'Donoghue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devicetree@vger.kernel.org, laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com References: <20260427-camss-isp-ope-v2-0-f430e7485009@oss.qualcomm.com> <20260427-camss-isp-ope-v2-2-f430e7485009@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260427-camss-isp-ope-v2-2-f430e7485009@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: uIpAl2KvhUha1RC5gAnzt49zvHouJc88 X-Proofpoint-ORIG-GUID: uIpAl2KvhUha1RC5gAnzt49zvHouJc88 X-Authority-Analysis: v=2.4 cv=DZEnbPtW c=1 sm=1 tr=0 ts=69ef6d08 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=s_dpPsJcIKQ2JMW1VggA:9 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDE0OSBTYWx0ZWRfX7h8D960aCy2h 3vNm2m+XRMCKEi+Cfuy+mlSB9zdLGVrF1BBEirxqCce6yY9irxp3Nxf3ff1ggrc6NOEgooH05h5 l6ZzfbumP1AZZwPugzPBIBb9ydHMeldP2IhTCJfPQ/xUFs1rVIAm8sszBZQANa36WiCIOichAVF gKwZWwuBLQCWecBEwvl/y9CYcXhp53hPDRhoJ3g4oCGmDXaBkPHhYOmfFJ9Cjs3opwVnqg4oqqy lFTZApSZvIKMSC6Rqj9NU60pUDB3Bpzj5QFGxSq5HhR2CeEf1ggDQU3LuxH9PlnXQe7hPJ7QeL+ 81lrptde1oXDjqpOg1vbZV57u/o+Huw6rUo+BXOoIrwCdyHLdl0T9dBbBWNeS8dFJzNxw17KL6Z tuX+zS7ytqIb06F971D6CVPTPXZsn2o/uz7f8vq7H/zcxxY82FA/bChV4/XZd2tGt2yFXbF54Dw HdSR5mk9f32ogecFNlQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-27_04,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270149 On 4/27/26 2:43 PM, Loic Poulain wrote: > Add optional PM clock support to the CAMSS driver using the PM clock > framework. This allows CAMSS clocks to be registered once and > automatically managed during runtime suspend and resume. > > This is especially useful for global CAMSS clocks that are shared across > multiple CAMSS subnodes. Now that CAMSS is modeled as a simple-bus, > these clocks are automatically enabled whenever a child node becomes > active. > > This avoids the need for each subdevice to reference and manage the > shared clocks individually. A typical example is the set of clocks in > the top_group, which may be used by CSID, PHY, CCI, OPE, and other > CAMSS blocks. > > Introduce a small PM clock descriptor table in the CAMSS resources > structure to describe clocks and their optional rates. Initialize > these clocks at probe time and delegate clock ownership to the PM > core. > > Hook PM clock handling into the runtime PM callbacks to ensure clocks > are properly suspended and resumed alongside power domains and ICC > paths. > > Signed-off-by: Loic Poulain > --- [...] > + for (i = 0; i < CAMSS_RES_MAX && camss->res->pm_clks[i].name; i++) { > + const struct camss_pm_clk *entry = &camss->res->pm_clks[i]; > + struct clk *clk; > + > + clk = clk_get(dev, entry->name); > + if (IS_ERR(clk)) { > + dev_warn(dev, "failed to get pm_clk %s: %pe\n", > + entry->name, clk); > + continue; > + } > + > + if (entry->rate) { > + ret = clk_set_rate(clk, entry->rate); > + if (ret) > + dev_warn(dev, "failed to set rate for pm_clk %s: %d\n", > + entry->name, ret); > + } So this makes a couple fragile assumptions: * there's only one "on/operational" rate * no OPP votes I would imagine that in the camss-is-the-bus model, the top-level device would house an OPP table.. but we have two somewhat independent clocks that may possibly have separate RPMH requirements for their M/N number of rates, which could result in M*N-long opp table Konrad