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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc73f102dsm336964566b.26.2026.02.17.03.23.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Feb 2026 03:23:03 -0800 (PST) Message-ID: Date: Tue, 17 Feb 2026 12:23:01 +0100 Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/3] Retrieve information about DDR from SMEM To: Connor Abbott , rob.clark@oss.qualcomm.com Cc: Konrad Dybcio , Bjorn Andersson , Kees Cook , "Gustavo A. R. Silva" , Sean Paul , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org References: <20260108-topic-smem_dramc-v3-0-6b64df58a017@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA5NSBTYWx0ZWRfX8H7Qv+IWIASa 4UWRfWVcY5q8TMsfGaCfKpuefHVZDGYWwMMgUc1zQpD0C7YHb9RtO/ZoBOJE/I8X0IcOV2tg4YG HvjbgT5uMCQAAFRpC+ZOI25XKvCQwxjPJ0RnCTwuAXgvZy42nPDaO1aMcT2rQNSeYLFF2U9KaRo Owfqel7R7iVZzl9Z4r2qkojT7I0/Md1e8v9Of6Ac2iyPEOjuGZ9f58PDmpu1sgPLkjWLapS15Pf BW1vLpl3d5jkjQhlmBIAoblP+fiXdx+rJlRkCm3dNGQ4+aglemAwTMLgpTQbUi7exVkABbaErH4 6eAy/nbU9mkGSxpIDI6e3hfTSC8raXHwAh6eXSrMGAov5Pa/kUP/U9/EmBiRGzYBshlaga1ykw5 /wj9l4CsiHTxQQxSE98OT1CQsHvL5f6v3iW4/r0ugCGf6L09M3LyUekogdG6bhd8QHq/ned0Y0E KKJJoqDECmWsBTtVh2w== X-Proofpoint-GUID: B-ccFq5AGkhjVpumEifPE2qRfeiQ-dAy X-Proofpoint-ORIG-GUID: B-ccFq5AGkhjVpumEifPE2qRfeiQ-dAy X-Authority-Analysis: v=2.4 cv=TPNIilla c=1 sm=1 tr=0 ts=69944f99 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=VwQbUJbxAAAA:8 a=cGCGxpJvRk8pEJ-QcToA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170095 On 1/9/26 10:03 PM, Connor Abbott wrote: > On Fri, Jan 9, 2026 at 3:41 PM Rob Clark wrote: >> >> On Fri, Jan 9, 2026 at 11:11 AM Connor Abbott wrote: >>> >>> On Thu, Jan 8, 2026 at 9:22 AM Konrad Dybcio wrote: >>>> >>>> SMEM allows the OS to retrieve information about the DDR memory. >>>> Among that information, is a semi-magic value called 'HBB', or Highest >>>> Bank address Bit, which multimedia drivers (for hardware like Adreno >>>> and MDSS) must retrieve in order to program the IP blocks correctly. >>>> >>>> This series introduces an API to retrieve that value, uses it in the >>>> aforementioned programming sequences and exposes available DDR >>>> frequencies in debugfs (to e.g. pass to aoss_qmp debugfs). More >>>> information can be exposed in the future, as needed. >>>> >>>> Patch 3 should really be merged after 1&2 >>> >>> No. The HBB value currently returned by the bootloader is *not* always >>> the same as what we use currently, because some SoCs (like SM8250) >>> with the same DT ship with multiple different DRAM configurations and >>> we've been using a sub-optimal value the whole time. After all, that's >>> the whole point of using the bootloader value. But patches 1&2 will >>> only make the DPU use the bootloader value for HBB, not the GPU. So on >>> one of the affected SoCs, it will introduce a mismatch. You can't >>> change anything until the GPU side uses the new ubwc config as its >>> source of truth. >> >> Hmm, how is this even working today if DPU is using HBB from the >> global table but GPU is not? Are we just getting lucky with >> compositors that don't know about modifiers and end up scanning out >> linear? > > It works out as well as it's always worked out, i.e. we try to make > GPU and DPU config match and pray that we didn't mess it up. At least > now we'll get a warning when they don't match. > >> >> We do log warnings when the global ubwc config does not match the >> "fixed up" config.. google search for those msgs doesn't seem to turn >> up anything other than the patch which introduced them. Idk if that >> is conclusive in any way, but I hope that means we could just delete >> the fixup code on the GPU side. I suppose we could add: >> >> *cfg = *common_cfg; >> >> after the warning as a first step. That would maybe get some bug >> reports along with enough details in dmesg? > > Yes, the plan was always to delete the fixup code in the GPU config. > And even that first step would be enough to prevent regressions when > switching to the bootloader HBB value. > > There is a problem in that ubwc_swizzle isn't as well tested. Older > parts supporting UBWC 1.0-3.0 partially or entirely ignore > ubwc_swizzle, because it wasn't configurable back then, but we rely on > it being set correctly in Mesa for VK_EXT_host_image_copy and sparse > textures. So if ubwc_swizzle is incorrect you probably wouldn't > notice, until you hit the HIC codepath in zink or some game using > sparse textures. I think we fixed up all the cases where it was > incorrectly set to 0x1 instead of 0x7, but it would be worth it to > check again. Just to double-check, is your expectation to just double-check the kernel settings, or would that require some intervention on the mesa side too? Konrad