From: Richard Kuo <rkuo@codeaurora.org>
To: linux-kernel@vger.kernel.org, linux-hexagon@vger.kernel.org
Cc: Linas Vepstas <linas@codeaurora.org>
Subject: [patch 24/36] Hexagon: Provide basic implementation and/or stubs for I/O routines.
Date: Wed, 17 Aug 2011 11:35:21 -0500 [thread overview]
Message-ID: <20110817163522.101836238@codeaurora.org> (raw)
In-Reply-To: 20110817163457.878854582@codeaurora.org
[-- Attachment #1: io.diff --]
[-- Type: text/plain, Size: 11482 bytes --]
Signed-off-by: Richard Kuo <rkuo@codeaurora.org>
Signed-off-by: Linas Vepstas <linas@codeaurora.org>
---
arch/hexagon/include/asm/io.h | 279 +++++++++++++++++++++++++++++++++++++++
arch/hexagon/include/asm/iomap.h | 30 ++++
arch/hexagon/lib/io.c | 91 ++++++++++++
3 files changed, 400 insertions(+)
Index: linux-hexagon-kernel/arch/hexagon/include/asm/io.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-hexagon-kernel/arch/hexagon/include/asm/io.h 2011-07-20 15:19:42.665151795 -0500
@@ -0,0 +1,279 @@
+/*
+ * IO definitions for the Hexagon architecture
+ *
+ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/vmalloc.h>
+#include <asm/string.h>
+#include <asm/mem-layout.h>
+#include <asm/iomap.h>
+#include <asm/page.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+/*
+ * Need to figure out where our I/O space is. Important for PCI.
+ * Which we don't have.
+ */
+#define IO_SPACE_LIMIT 0xffffffff
+#define _IO_BASE 0x0
+
+extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
+ unsigned long end, unsigned long flags);
+
+extern void __iounmap(const volatile void __iomem *addr);
+
+/* Defined in lib/io.c, needed for smc91x driver. */
+extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
+extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
+
+extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen);
+extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen);
+
+#define readsw(p, d, l) __raw_readsw(p, d, l)
+#define writesw(p, d, l) __raw_writesw(p, d, l)
+
+#define readsl(p, d, l) __raw_readsl(p, d, l)
+#define writesl(p, d, l) __raw_writesl(p, d, l)
+
+/*
+ * virt_to_phys - map virtual address to physical
+ * @address: address to map
+ */
+static inline unsigned long virt_to_phys(volatile void *address)
+{
+ return __pa(address);
+}
+
+/*
+ * phys_to_virt - map physical address to virtual
+ * @address: address to map
+ */
+static inline void *phys_to_virt(unsigned long address)
+{
+ return __va(address);
+}
+
+/*
+ * IO port access primitives. Hexagon doesn't have special IO access
+ * instructions; all I/O is memory mapped.
+ *
+ * in/out are used for "ports", but we don't have "port instructions",
+ * so these are really just memory mapped too.
+ */
+
+/*
+ * readb - read byte from memory mapped device
+ * @addr: pointer to memory
+ *
+ * Operates on "I/O bus memory space"
+ */
+static inline u8 readb(const volatile void __iomem *addr)
+{
+ const volatile u8 *__mem = addr;
+ u8 val = *__mem;
+ return val;
+}
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+ const volatile u16 *__mem = addr;
+ u16 val = *__mem;
+ return val;
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+ const volatile u32 *__mem = addr;
+ u32 val = *__mem;
+ return val;
+}
+
+/*
+ * inb - read byte from I/O port or something
+ * @port: address in I/O space
+ *
+ * Operates on "I/O bus I/O space"
+ */
+static inline u8 inb(unsigned long port)
+{
+ printk(KERN_INFO "inb not implemented\n");
+ return 0;
+}
+
+static inline u16 inw(unsigned long port)
+{
+ printk(KERN_INFO "inw not implemented\n");
+ return 0;
+}
+
+static inline u32 inl(unsigned long port)
+{
+ printk(KERN_INFO "inl not implemented\n");
+ return 0;
+}
+
+/*
+ * writeb - write a byte to a memory location
+ * @data: data to write to
+ * @addr: pointer to memory
+ *
+ */
+static inline void writeb(u8 data, volatile void __iomem *addr)
+{
+ volatile u8 *__mem = addr;
+ *__mem = data;
+ return;
+}
+
+static inline void writew(u16 data, volatile void __iomem *addr)
+{
+ volatile u16 *__mem = addr;
+ *__mem = data;
+ return;
+}
+
+static inline void writel(u32 data, volatile void __iomem *addr)
+{
+ volatile u32 *__mem = addr;
+ *__mem = data;
+ return;
+}
+
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+
+#define PCI_IO_ADDR volatile void __iomem *
+
+/*
+ * outb - write a byte to a memory location
+ * @data: data to write to
+ * @addr: address in I/O space
+ */
+static inline void outb(u8 data, unsigned long port)
+{
+ writeb(data, (PCI_IO_ADDR)_IO_BASE+port);
+}
+
+static inline void outw(u16 data, unsigned long port)
+{
+ writew(data, (PCI_IO_ADDR)_IO_BASE+port);
+}
+
+static inline void outl(u32 data, unsigned long port)
+{
+ writel(data, (PCI_IO_ADDR)_IO_BASE+port);
+}
+
+/*
+ * Need an mtype somewhere in here, for cache type deals?
+ * This is probably too long for an inline.
+ */
+void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size);
+
+static inline void __iomem *ioremap(unsigned long phys_addr, unsigned long size)
+{
+ return ioremap_nocache(phys_addr, size);
+}
+
+static inline void iounmap(volatile void __iomem *addr)
+{
+ __iounmap(addr);
+}
+
+#define __raw_writel writel
+
+/* _p means "pause until the I/O completes" */
+#define outb_p outb
+#define outw_p outw
+#define outl_p outl
+
+#define inb_p inb
+#define inw_p inw
+#define inl_p inl
+
+static inline void insb(unsigned long addr, void *buffer, int count)
+{
+ printk(KERN_INFO "insb not implemented\n");
+}
+
+static inline void insw(unsigned long addr, void *buffer, int count)
+{
+ printk(KERN_INFO "insw not implemented\n");
+}
+
+static inline void insl(unsigned long addr, void *buffer, int count)
+{
+ printk(KERN_INFO "insl not implemented\n");
+}
+
+static inline void outsb(unsigned long addr, const void *buffer, int count)
+{
+ printk(KERN_INFO "outsb not implemented\n");
+}
+
+static inline void outsw(unsigned long addr, const void *buffer, int count)
+{
+ printk(KERN_INFO "outsw not implemented\n");
+}
+
+static inline void outsl(unsigned long addr, const void *buffer, int count)
+{
+ printk(KERN_INFO "outsl not implemented\n");
+}
+
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
+ int count)
+{
+ memcpy(dst, (void *) src, count);
+}
+
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
+ int count)
+{
+ memcpy((void *) dst, src, count);
+}
+
+/*
+ * convert a physical pointer to a virtual kernel pointer for
+ * /dev/mem access.
+ */
+#define xlate_dev_kmem_ptr(p) __va(p)
+#define xlate_dev_mem_ptr(p) __va(p)
+
+/* generic versions defined in lib/iomap.c */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *addr);
+
+#define flush_write_buffers() do { } while (0)
+
+#endif /* __KERNEL__ */
+
+#endif
Index: linux-hexagon-kernel/arch/hexagon/lib/io.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-hexagon-kernel/arch/hexagon/lib/io.c 2011-07-20 15:19:42.665151795 -0500
@@ -0,0 +1,91 @@
+/*
+ * I/O access functions for Hexagon
+ *
+ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <asm/io.h>
+
+/* These are all FIFO routines! */
+
+/*
+ * __raw_readsw - read words a short at a time
+ * @addr: source address
+ * @data: data address
+ * @len: number of shorts to read
+ */
+void __raw_readsw(const void __iomem *addr, void *data, int len)
+{
+ const volatile short int *src = (short int *) addr;
+ short int *dst = (short int *) data;
+
+ if ((u32)data & 0x1)
+ panic("unaligned pointer to readsw");
+
+ while (len-- > 0)
+ *dst++ = *src;
+
+}
+
+/*
+ * __raw_writesw - read words a short at a time
+ * @addr: source address
+ * @data: data address
+ * @len: number of shorts to read
+ */
+void __raw_writesw(void __iomem *addr, const void *data, int len)
+{
+ const short int *src = (short int *)data;
+ volatile short int *dst = (short int *)addr;
+
+ if ((u32)data & 0x1)
+ panic("unaligned pointer to writesw");
+
+ while (len-- > 0)
+ *dst = *src++;
+
+
+}
+
+/* Pretty sure len is pre-adjusted for the length of the access already */
+void __raw_readsl(const void __iomem *addr, void *data, int len)
+{
+ const volatile long *src = (long *) addr;
+ long *dst = (long *) data;
+
+ if ((u32)data & 0x3)
+ panic("unaligned pointer to readsl");
+
+ while (len-- > 0)
+ *dst++ = *src;
+
+
+}
+
+void __raw_writesl(void __iomem *addr, const void *data, int len)
+{
+ const long *src = (long *)data;
+ volatile long *dst = (long *)addr;
+
+ if ((u32)data & 0x3)
+ panic("unaligned pointer to writesl");
+
+ while (len-- > 0)
+ *dst = *src++;
+
+
+}
Index: linux-hexagon-kernel/arch/hexagon/include/asm/iomap.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-hexagon-kernel/arch/hexagon/include/asm/iomap.h 2011-07-20 15:19:42.665151795 -0500
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef _HEXAGON_IOMAP_H
+#define _HEXAGON_IOMAP_H
+
+#ifndef __ASSEMBLY__
+#include <asm-generic/iomap.h>
+#endif
+
+#ifdef CONFIG_HEXAGON_COMET
+#include "platform/comet/comet_iomap.h"
+#endif
+
+#endif
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2011-08-17 16:35 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-17 16:34 [patch 00/36] Hexagon: Add support for Qualcomm Hexagon architecture Richard Kuo
2011-08-17 16:34 ` [patch 01/36] Hexagon: Add generic headers Richard Kuo
2011-08-17 19:19 ` Arnd Bergmann
2011-08-17 16:34 ` [patch 02/36] Hexagon: Core arch-specific header files Richard Kuo
2011-08-17 19:19 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 03/36] Hexagon: Add bitops support Richard Kuo
2011-08-17 19:19 ` Arnd Bergmann
2011-08-26 20:34 ` Pavel Machek
2011-08-30 21:14 ` ARM assembly syntax (was Re: [patch 03/36] Hexagon: Add bitops support) Linas Vepstas (Code Aurora)
2011-09-02 16:53 ` Pavel Machek
2011-08-17 16:35 ` [patch 04/36] Hexagon: Add atomic ops support Richard Kuo
2011-08-17 19:20 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 05/36] Hexagon: Add syscalls Richard Kuo
2011-08-17 19:29 ` Arnd Bergmann
2011-08-17 20:12 ` Jonas Bonn
2011-08-17 16:35 ` [patch 06/36] Hexagon: Add processor and system headers Richard Kuo
2011-08-17 19:31 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 07/36] Hexagon: Add threadinfo Richard Kuo
2011-08-17 19:37 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 08/36] Hexagon: Add delay functions Richard Kuo
2011-08-17 19:38 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 09/36] Hexagon: Add checksum functions Richard Kuo
2011-08-17 19:40 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 10/36] Hexagon: Add memcpy and memset accelerated functions Richard Kuo
2011-08-17 16:35 ` [patch 11/36] Hexagon: Add hypervisor interface Richard Kuo
2011-08-17 16:35 ` [patch 12/36] Hexagon: Export ksyms defined in assembly files Richard Kuo
2011-08-17 16:35 ` [patch 13/36] Hexagon: Support dynamic module loading Richard Kuo
2011-08-17 19:41 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 14/36] Hexagon: Add signal functions Richard Kuo
2012-02-11 23:27 ` hexagon: signal handling bugs Al Viro
2012-02-15 17:45 ` Richard Kuo
2012-02-15 18:18 ` Linas Vepstas
2011-08-17 16:35 ` [patch 15/36] Hexagon: Add init_task and process functions Richard Kuo
2011-08-17 19:45 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 16/36] Hexagon: Add startup code Richard Kuo
2011-08-17 16:35 ` [patch 17/36] Hexagon: Add interrupts Richard Kuo
2011-08-17 16:35 ` [patch 18/36] Hexagon: Add time and timer functions Richard Kuo
2011-08-17 16:35 ` [patch 19/36] Hexagon: Add ptrace support Richard Kuo
2011-08-17 19:47 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 20/36] Hexagon: Provide basic debugging and system trap support Richard Kuo
2011-08-17 16:35 ` [patch 21/36] Hexagon: Add SMP support Richard Kuo
2011-08-17 16:35 ` [patch 22/36] Hexagon: Add locking types and functions Richard Kuo
2011-08-17 16:35 ` [patch 23/36] Hexagon: Add user access functions Richard Kuo
2011-08-17 16:35 ` Richard Kuo [this message]
2011-08-17 19:55 ` [patch 24/36] Hexagon: Provide basic implementation and/or stubs for I/O routines Arnd Bergmann
2011-08-17 16:35 ` [patch 25/36] Hexagon: Implement basic cache-flush support Richard Kuo
2011-08-17 16:35 ` [patch 26/36] Hexagon: Implement basic TLB management routines for Hexagon Richard Kuo
2011-08-17 16:35 ` [patch 27/36] Hexagon: Provide DMA implementation Richard Kuo
2011-08-17 20:01 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 28/36] Hexagon: Add ioremap support Richard Kuo
2011-08-17 16:35 ` [patch 29/36] Hexagon: Add page table header files & etc Richard Kuo
2011-08-17 16:35 ` [patch 30/36] Hexagon: Add page-fault support Richard Kuo
2011-08-17 16:35 ` [patch 31/36] Hexagon: kgdb support files Richard Kuo
2011-08-17 16:35 ` [patch 32/36] Hexagon: Comet platform support Richard Kuo
2011-08-17 20:07 ` Arnd Bergmann
2011-08-17 23:45 ` Linas Vepstas
2011-08-17 20:08 ` David Brown
2011-08-17 16:35 ` [patch 33/36] Hexagon: Platform-generic support Richard Kuo
2011-08-17 20:20 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 34/36] Hexagon: Add configuration and makefiles for the Hexagon architecture Richard Kuo
2011-08-17 20:27 ` Arnd Bergmann
2011-08-17 16:35 ` [patch 35/36] Hexagon: Add basic stacktrace functionality for " Richard Kuo
2011-08-17 16:35 ` [patch 36/36] Hexagon: Add self to MAINTAINERS Richard Kuo
2011-08-17 19:00 ` [patch 00/36] Hexagon: Add support for Qualcomm Hexagon architecture Zan Lynx
2011-08-17 19:42 ` Richard Kuo
2011-08-17 20:34 ` Arnd Bergmann
2011-08-18 0:31 ` Richard Kuo
2011-08-31 5:48 ` Avi Kivity
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