From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: common non-cache coherent direct dma mapping ops Date: Fri, 11 May 2018 09:59:25 +0200 Message-ID: <20180511075945.16548-1-hch@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=4wx5mKm3C3YIokHdRKpACvmtVmKY5sD2XUoq4d8zIhw=; b=hgo 9kH976usDgVuwCXGaqJH0oATyQa5r1lA7h4NkDKT5wcukqf3zkJ+pk7GzdR7fsl/RpPi9IZ9wjbBR iDPQtku5k6nwiXFuqJKE3Y+tuXSmbjmBu8e0hAsoXPuRdgvshgI7IMb21hZCsw8skOctfzqZXxsqh h+kKKubakZ1WiL6H6IOj/X85sM8St/+2W1sDqrUSNufsp7ER2Y3jKuo2TEM/LS2FQ16doBcq8M7Pe 2mtEufIwQjEOBnbpJXVXFcWF3FRXMTilYVS+g6H4zVv24TKLsKhaMSBpZ95YLnegHc4RQldnRF7Zw P1BeCwAsG4AWIXU9PhKyuC64u+LjKVg==; List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+gla-linux-snps-arc=m.gmane.org@lists.infradead.org To: iommu@lists.linux-foundation.org Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org, Michal Simek , Vincent Chen , linux-c6x-dev@linux-c6x.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, openrisc@lists.librecores.org, Greentime Hu , linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, nios2-dev@lists.rocketboards.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org Hi all, this series continues consolidating the dma-mapping code, with a focus on architectures that do not (always) provide cache coherence for DMA. Three architectures (arm, mips and powerpc) are still left to be converted later due to complexity of their dma ops selection. The dma-noncoherent ops calls the dma-direct ops for the actual translation of streaming mappins and allow the architecture to provide any cache flushing required for cpu to device and/or device to cpu ownership transfers. The dma coherent allocator is for now still left entirely to architecture supplied implementations due the amount of variations. Hopefully we can do some consolidation for them later on as well. A lot of architectures are currently doing very questionable things in their dma mapping routines, which are documented in the changelogs for each patch. Please review them very careful and correct me on incorrect assumptions. Because this series sits on top of two previously submitted series a git tree might be useful to actually test it. It is provided here: git://git.infradead.org/users/hch/misc.git generic-dma-noncoherent Gitweb: http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/generic-dma-noncoherent Changes since RFC: - fix a typo accidentally disabling the device to cpu transfer sync - fixed a few compile failures