From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Hildenbrand Subject: Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Date: Tue, 28 Feb 2023 16:55:41 +0100 Message-ID: <5d99c731-c47a-c525-76e5-4578d9dfc9ee@redhat.com> References: <20230113171026.582290-1-david@redhat.com> <20230113171026.582290-12-david@redhat.com> <9ed766a6-cf06-535d-3337-ea6ff25c2362@redhat.com> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Return-path: DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oiiLgXRX3yNx2zDFX6lwaIfWYFgfGz9CfZko3gAcRnc=; b=qy6AVRKTtH7hmT wrny2fpjpSCG/Hcmy6P6UwFXGb7wyAm9nVt5R4qcegeHhNoBL3kTKdVaYLpkU13mXQK0z2YIaCsmp XfYzaRAXK1boHYjCJz8bsRTDZ+Zkx4W8nVXYZJ2S52ya6EKYwfzZgosUNPvdzSo95Fjs0LiiRik9V zyLIgju4YLp7+59KRKDAvSgyGRkdVhBIDJMeuRxg5HZTWv7N8O8nepXO2z016RsUs8sc+KO8+Apqf c489q8ZOYONeTyYwxDNhHH86HAF3XykaFzIqrwOsr2FBm4GpTN59Dg412VCc+0YiOy6FO15fPAFYY mEeS2n0EAWYvDWLyN8OQ==; DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1677599745; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xBghEncF8boHA8ERPg4saQyYB+zKBnxfff7p7OTCduA=; b=BNjjPB2dZvKhbiImD/+DnoZeWXleedN/vFDEYvTrr+o4gMYCf+OkNlmx7IzBN9Yy+lqb0z in0Yq0NxPJHLBMpZliuVTtJJaC9M3611P5dKFopDjrlKNCI1myqf64SRQkOkSF9S7P4uXR ftjkol/HTHt/0ZaojciVyvb8CHiYXm8= In-Reply-To: Content-Language: en-US List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+glpr-linux-riscv=m.gmane-mx.org@lists.infradead.org Content-Type: text/plain; charset="us-ascii"; format="flowed" To: Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , John Hubbard , Jason Gunthorpe , Mike Rapoport , Yang Shi , Vlastimil Babka , Nadav Amit , Andrea Arcangeli , Peter Xu , linux-mm@kvack.org, x86@kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, On 27.02.23 20:46, Geert Uytterhoeven wrote: > Hi David, > > On Mon, Feb 27, 2023 at 6:01 PM David Hildenbrand wrote: >>>>>> /* >>>>>> * Externally used page protection values. >>>>>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h >>>>>> index 42f5988e998b..7e3de54bf426 100644 >>>>>> --- a/arch/microblaze/include/asm/pgtable.h >>>>>> +++ b/arch/microblaze/include/asm/pgtable.h > >>>>>> * - All other bits of the PTE are loaded into TLBLO without >>>>>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for >>>>>> * software PTE bits. We actually use bits 21, 24, 25, and >>>>>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); >>>>>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ >>>>>> #define _PMD_PRESENT PAGE_MASK >>>>>> >>>>>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ >>>>>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY >>>>> >>>>> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is >>>>> wrong? >>>> >>>> In the example, I use MSB-0 bit numbering (which I determined to be >>>> correct in microblaze context eventually, but I got confused a couple a >>>> times because it's very inconsistent). That should be MSB-0 bit 24. >>> >>> Thanks, TIL microblaze uses IBM bit numbering... >> >> I assume IBM bit numbering corresponds to MSB-0 bit numbering, correct? > > Correct, as seen in s370 and PowerPC manuals... Good, I have some solid s390x background, but thinking about the term "IBM PC" made me double-check that we're talking about the same thing ;) > >> I recall that I used the comment above "/* Definitions for MicroBlaze. >> */" as an orientation. >> >> 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 >> RPN..................... 0 0 EX WR ZSEL....... W I M G > > Indeed, that's where I noticed the "unconventional" numbering... > >> So ... either we adjust both or we leave it as is. (again, depends on >> what the right thing to to is -- which I don't know :) ) > > It depends whether you want to match the hardware documentation, > or the Linux BIT() macro and friends... The hardware documentation, so we should be good. Thanks! -- Thanks, David / dhildenb