From: Matthew Wilcox <matthew@wil.cx>
To: linux-hotplug@vger.kernel.org
Subject: Re: [Pcihpd-discuss] Fwd: what is the pcie capability base for a configure process
Date: Mon, 29 May 2006 04:20:54 +0000 [thread overview]
Message-ID: <20060529042054.GD23405@parisc-linux.org> (raw)
On Mon, May 29, 2006 at 11:30:07AM +0800, william wallace wrote:
> I am reading ur code for pcie configuration registers and
> configuration process for linux kenerl 2.6.9,really elegant,but
> stillsomething confuse me :
> 1 :why the starting location for pcie capability base is 0?
> what is the absolute offset for the capability register?
> --------------------------pcie_cap_base = 0; in pciehp_hpc.c
pcie_cap_base looks like a vestige of some earlier code and should
simply be removed, along with saved_cap_base.
> 2:what is the mechanism for read/write config space
> #define hp_register_read_word(pdev, reg , value) \
> pci_read_config_word(pdev, reg, &value)
> going down ,i get the pci_bus_read_config_word,so ,where is the real guts?
> thank u!
drivers/pci/access.c They're constructed, which is why you can't grep for
them. Of course, the low-level accessors are defined per-architecture,
sometimes in several different ways, depending on what bus is being
accessed.
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next reply other threads:[~2006-05-29 4:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-05-29 4:20 Matthew Wilcox [this message]
2006-05-29 4:44 ` [Pcihpd-discuss] Fwd: what is the pcie capability base for a configure process william wallace
2006-05-29 6:45 ` william wallace
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