From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthew Wilcox Date: Mon, 29 May 2006 04:20:54 +0000 Subject: Re: [Pcihpd-discuss] Fwd: what is the pcie capability base for a configure process Message-Id: <20060529042054.GD23405@parisc-linux.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-hotplug@vger.kernel.org On Mon, May 29, 2006 at 11:30:07AM +0800, william wallace wrote: > I am reading ur code for pcie configuration registers and > configuration process for linux kenerl 2.6.9,really elegant,but > stillsomething confuse me : > 1 :why the starting location for pcie capability base is 0? > what is the absolute offset for the capability register? > --------------------------pcie_cap_base = 0; in pciehp_hpc.c pcie_cap_base looks like a vestige of some earlier code and should simply be removed, along with saved_cap_base. > 2:what is the mechanism for read/write config space > #define hp_register_read_word(pdev, reg , value) \ > pci_read_config_word(pdev, reg, &value) > going down ,i get the pci_bus_read_config_word,so ,where is the real guts? > thank u! drivers/pci/access.c They're constructed, which is why you can't grep for them. Of course, the low-level accessors are defined per-architecture, sometimes in several different ways, depending on what bus is being accessed. ------------------------------------------------------- All the advantages of Linux Managed Hosting--Without the Cost and Risk! Fully trained technicians. The highest number of Red Hat certifications in the hosting industry. Fanatical Support. Click to learn more http://sel.as-us.falkag.net/sel?cmd=lnk&kid7521&bid$8729&dat1642 _______________________________________________ Linux-hotplug-devel mailing list http://linux-hotplug.sourceforge.net Linux-hotplug-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/linux-hotplug-devel