Re: PCI Enumeration problem during hotswap

[Scott Murray <scottm@somanetworks.com>]

On 11 Jul 2003, Nikunj A. Dadhania wrote:

> Hello,
> 
> I have been trying to run Hotswap on 2.4.18 on one of the CPCI boards. I
> have back ported the 2.4.19 hotswap patch to 2.4.18 kernel. Also written
> the necessary driver for the hotswap code. 
> 
> This board is a x86 board with Serverworks(GCSL) chipsets

Any chance I could get a copy of the board specific driver for potential 
inclusion in 2.5 (and my standalone 2.4 patchset)?

> Observations:
> 
> * Allocating resources(PCI MEM and IO bars) to the PCI devices in the
> correct PCI memory range. 
> 
> Below three are related to the Hostbridge to forward PCI memory
> transaction to the bus beyond.
> * Programmed correct Memory hole registers on Host Bridge
> * Programmed correct Memory Region 0 upper and lower register in Host
> bridge
> * Enabled Memory Region 0 in PMRR register
> 
> * Programmed the South Bridge to route the interrupts correctly to CPU

I'm interested in how you obtained the documentation to know how to do 
this, since I'm just starting the process of talking to Serverworks 
myself.  Did Serverworks provide it to you, and if so, did it take much
effort to get it?

> * E1000 device on the CPCI is being detected and the driver picks up
> correct MAC address from the ROM. It also detects the link up/down
> * E1000's command registers are fine
> 
> * E1000 is not able to transmit packets on the line. Get an error
> "NETDEV WATCHDOG: transmit timed out" and then resets the device.
> 
> * Close observation revealed that the driver is receiving some packets
> from the line, all of them are erroneous and so dropped and never
> delivered to upper layer.
> 
> * Tried connecting PCI analyser on the CPCI bus and could see the memory
> transaction on the bus.
> 
> Could someone help with this:
> 
> The problem is I am not able to ping using E1000. 
> 
> Same E1000 device works if the CPCI board is not hotswapped and BIOS is
> doing the PCI enumeration.
> 
> Am I missing something very obvious?

Is the e1000 chip being assigned an interrupt?  It kind of looks like the 
GC-SL chipset has an integrated IO-APIC, and interrupt assignment will
not work on systems with an IO-APIC without some changes to the file 
arch/i386/kernel/pci-irq.c (that I can provide if necessary).  The other 
potential problem if it has an IO-APIC is that the MP table the BIOS 
writes out likely does not have entries for slots that do not have 
peripheral cards in them at boot time, with the end result that hot-insert 
into an originally empty slot does not work (but hot-replace works).  I 
don't have a clean fix for this problem at the moment, unfortunately; my 
workaround for the Motorola XIP68 board involves hacking the MP table 
parser.

> If required I can send the dumps of lspci.

The output of "lspci -tv" as well as "lspci -vvv" before and after 
inserting the e1000 peripheral board would be helpful, as would the 
output of dmesg after inserting your peripheral board after loading the 
cpci_hotplug_core.o module with debug=1.  One of the other debugging 
techniques that I've found helpful is to modify pci-i386.h in
arch/i386/kernel to #define DEBUG, which enables some more debugging 
output in a bunch of the core PCI routines.

As a final note, this discussion is probably better suited to the 
pcihpd-discuss@lists.sourceforge.net mailing list, which I'm CC'ing.  The 
regular hotplug folk would probably appreciate being pruned out of future 
discussion.

Scott


-- 
Scott Murray
SOMA Networks, Inc.
Toronto, Ontario
e-mail: scottm@somanetworks.com





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