Re: [PATCH v3 3/3] dt-bindings: sbrmi: Add SB-RMI hwmon driver bindings

Guenter Roeck
2021-07-25T21:37:01Z

On 7/19/21 10:57 PM, Naveen Krishna Chatradhi wrote:
> From: Akshay Gupta <Akshay.Gupta@amd.com>
>
> - Document device tree bindings for AMD SB-RMI emulated service.
>
> Signed-off-by: Akshay Gupta <Akshay.Gupta@amd.com>
> Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>

Devicetree files need to be approved by a dt maintainer.
They can't do that if they are not copied on devicetree patches.

Guenter

> ---
> Changes since v2:
> None
>
> .../devicetree/bindings/hwmon/amd,sbrmi.yaml | 53 +++++++++++++++++++
> 1 file changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml b/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml
> new file mode 100644
> index 000000000000..7598b083979c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/hwmon/amd,sbrmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: >
> + Sideband Remote Management Interface (SB-RMI) compliant
> + AMD SoC power device.
> +
> +maintainers:
> + - Akshay Gupta <Akshay.Gupta@amd.com>
> +
> +description: |
> + SB Remote Management Interface (SB-RMI) is an SMBus compatible
> + interface that reports AMD SoC's Power (normalized Power) using,
> + Mailbox Service Request and resembles a typical 8-pin remote power
> + sensor's I2C interface to BMC. The power attributes in hwmon
> + reports power in microwatts.
> +
> +properties:
> + compatible:
> + enum:
> + - amd,sbrmi
> +
> + reg:
> + maxItems: 1
> + description: |
> + I2C bus address of the device as specified in Section SBI SMBus Address
> + of the SoC register reference. The SB-RMI address is normally 78h for
> + socket 0 and 70h for socket 1, but it could vary based on hardware
> + address select pins.
> + \[open source SoC register reference\]
> + https://www.amd.com/en/support/tech-docs?keyword=55898
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + i2c0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sbrmi@3c {
> + compatible = "amd,sbrmi";
> + reg = <0x3c>;
> + };
> + };
> +...
>