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Mon, 14 Oct 2024 12:12:05 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id QNquLpUKDWf9PAAAD6G6ig (envelope-from ); Mon, 14 Oct 2024 12:12:05 +0000 Date: Mon, 14 Oct 2024 14:12:04 +0200 From: Jean Delvare To: Guenter Roeck Cc: Hardware Monitoring Subject: Re: [PATCH] hwmon: (jc42) Strengthen detect function Message-ID: <20241014141204.026f4641@endymion.delvare> In-Reply-To: <20240630202028.1874325-1-linux@roeck-us.net> References: <20240630202028.1874325-1-linux@roeck-us.net> Organization: SUSE Linux X-Mailer: Claws Mail 4.1.1 (GTK 3.24.34; x86_64-suse-linux-gnu) Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Spam-Score: -4.30 X-Spamd-Result: default: False [-4.30 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCPT_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; HAS_ORG_HEADER(0.00)[]; ARC_NA(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; FUZZY_BLOCKED(0.00)[rspamd.com]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; MIME_TRACE(0.00)[0:+] X-Spam-Flag: NO X-Spam-Level: Hi Guenter, On Sun, 30 Jun 2024 13:20:28 -0700, Guenter Roeck wrote: > Configuration register bit 5 must read 0 for all JC42.4 compliant chips. > Several capability register bits must be set for all TSE2004 compliant > chips. Use that information to strengthen the detect function. > > Signed-off-by: Guenter Roeck > --- > drivers/hwmon/jc42.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c > index 1180af1b1638..a260cff750a5 100644 > --- a/drivers/hwmon/jc42.c > +++ b/drivers/hwmon/jc42.c > @@ -413,7 +413,11 @@ static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info) > if (cap < 0 || config < 0 || manid < 0 || devid < 0) > return -ENODEV; > > - if ((cap & 0xff00) || (config & 0xf800)) > + if ((cap & 0xff00) || (config & 0xf820)) > + return -ENODEV; > + > + if ((devid & TSE2004_DEVID_MASK) == TSE2004_DEVID && > + (cap & 0x00e7) != 0x00e7) > return -ENODEV; > > for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) { I have a user reporting that this change is causing the jc42 driver to no longer bind to his memory module temperature sensor devices after updating to kernel v6.11. I asked for a register dump: 0,8 1,9 2,a 3,b 4,c 5,d 6,e 7,f 00: 7f00 0000 0000 0000 0000 6ac2 091b 3022 After swapping the bytes, I see that this is a TSE2004-compliant device (devid = 0x2230) and the capabilities register reads 0x007f. This doesn't pass the 0x00e7 mask test you added, as bit 7 isn't set in his case. The JEDEC standard indeed says that bit 7 should be set, but apparently this isn't always the case in the real world. Also note that I looked at the Renesas TSE2004GB2B0 datasheet and it shows bit 2 (RANGE) as not always set. The ST STTS2004 datasheet shows bits 0 (EVENT) and 2 (RANGE) as possibly reading 0. So I wonder how much we can rely on these capability bits being set in the detect function. Unfortunately I don't have any TS2004-compliant device at hand to verify, nor do I own register dumps of such devices. Would it be OK with you if we relax the check to at least ignore bit 7, and possibly also bits 0 and 2? Thanks, -- Jean Delvare SUSE L3 Support