diff for duplicates of <20250303105902.215009-10-akshay.gupta@amd.com> diff --git a/a/1.txt b/N1/1.txt index 37020f3..4c4ce80 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,230 +1,3 @@ - AMD provides custom protocol to read Machine Check Architecture(MCA) registers over sideband. The information is accessed for range of - MCA registers by passing register address and thread ID to the protocol. - MCA register read command using the register address to access - Core::X86::Msr::MCG_CAP which determines the number of MCA banks. - Access is read-only - -Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> -Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> ---- -Changes since v4: -- Previously patch 7 -- Address review comment for documentation warning - -Changes since v3: -- Address review comments: - - update the #define to inline function - - pack the union inside the structure - -Changes since v2: -- update the MACROS name as per feedback - -Changes since v1: -- bifurcated from previous patch 5 - - drivers/misc/amd-sbi/rmi-core.c | 100 ++++++++++++++++++++++++++++++++ - include/uapi/misc/amd-apml.h | 18 ++++-- - 2 files changed, 112 insertions(+), 6 deletions(-) - -diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c -index 6fd6e8e579d5..662aa90980fc 100644 ---- a/drivers/misc/amd-sbi/rmi-core.c -+++ b/drivers/misc/amd-sbi/rmi-core.c -@@ -30,10 +30,16 @@ - #define CPUID_WR_DATA_LEN 0x8 - #define CPUID_RD_REG_LEN 0xa - #define CPUID_WR_REG_LEN 0x9 -+/* MSR */ -+#define MSR_RD_REG_LEN 0xa -+#define MSR_WR_REG_LEN 0x8 -+#define MSR_RD_DATA_LEN 0x8 -+#define MSR_WR_DATA_LEN 0x7 - - /* CPUID MSR Command Ids */ - #define CPUID_MCA_CMD 0x73 - #define RD_CPUID_CMD 0x91 -+#define RD_MCA_CMD 0x86 - - /* input for bulk write to CPUID protocol */ - struct cpu_msr_indata { -@@ -70,6 +76,16 @@ static inline void prepare_cpuid_input_message(struct cpu_msr_indata *input, - input->ext = ext_func; - } - -+static inline void prepare_mca_msr_input_message(struct cpu_msr_indata *input, -+ u8 thread_id, u32 data_in) -+{ -+ input->rd_len = MSR_RD_DATA_LEN; -+ input->wr_len = MSR_WR_DATA_LEN; -+ input->proto_cmd = RD_MCA_CMD; -+ input->thread = thread_id << 1; -+ input->value = data_in; -+} -+ - static int sbrmi_get_rev(struct sbrmi_data *data) - { - struct apml_message msg = { 0 }; -@@ -167,6 +183,86 @@ static int rmi_cpuid_read(struct sbrmi_data *data, - return ret; - } - -+/* MCA MSR protocol */ -+static int rmi_mca_msr_read(struct sbrmi_data *data, -+ struct apml_message *msg) -+{ -+ struct cpu_msr_outdata output = {0}; -+ struct cpu_msr_indata input = {0}; -+ int ret, val = 0; -+ int hw_status; -+ u16 thread; -+ -+ mutex_lock(&data->lock); -+ /* cache the rev value to identify if protocol is supported or not */ -+ if (!data->rev) { -+ ret = sbrmi_get_rev(data); -+ if (ret < 0) -+ goto exit_unlock; -+ } -+ /* MCA MSR protocol for REV 0x10 is not supported*/ -+ if (data->rev == 0x10) { -+ ret = -EOPNOTSUPP; -+ goto exit_unlock; -+ } -+ -+ thread = msg->data_in.reg_in[AMD_SBI_THREAD_LOW_INDEX] | -+ msg->data_in.reg_in[AMD_SBI_THREAD_HI_INDEX] << 8; -+ -+ /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */ -+ if (thread > 127) { -+ thread -= 128; -+ val = 1; -+ } -+ ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val); -+ if (ret < 0) -+ goto exit_unlock; -+ -+ prepare_mca_msr_input_message(&input, thread, -+ msg->data_in.mb_in[AMD_SBI_RD_WR_DATA_INDEX]); -+ -+ ret = regmap_bulk_write(data->regmap, CPUID_MCA_CMD, -+ &input, MSR_WR_REG_LEN); -+ if (ret < 0) -+ goto exit_unlock; -+ -+ /* -+ * For RMI Rev 0x20, new h/w status bit is introduced. which is used -+ * by firmware to indicate completion of commands (0x71, 0x72, 0x73). -+ * wait for the status bit to be set by the hardware before -+ * reading the data out. -+ */ -+ ret = regmap_read_poll_timeout(data->regmap, SBRMI_STATUS, hw_status, -+ hw_status & HW_ALERT_MASK, 500, 2000000); -+ if (ret) -+ goto exit_unlock; -+ -+ ret = regmap_bulk_read(data->regmap, CPUID_MCA_CMD, -+ &output, MSR_RD_REG_LEN); -+ if (ret < 0) -+ goto exit_unlock; -+ -+ ret = regmap_write(data->regmap, SBRMI_STATUS, -+ HW_ALERT_MASK); -+ if (ret < 0) -+ goto exit_unlock; -+ -+ if (output.num_bytes != MSR_RD_REG_LEN - 1) { -+ ret = -EMSGSIZE; -+ goto exit_unlock; -+ } -+ if (output.status) { -+ ret = -EPROTOTYPE; -+ msg->fw_ret_code = output.status; -+ goto exit_unlock; -+ } -+ msg->data_out.cpu_msr_out = output.value; -+ -+exit_unlock: -+ mutex_unlock(&data->lock); -+ return ret; -+} -+ - int rmi_mailbox_xfer(struct sbrmi_data *data, - struct apml_message *msg) - { -@@ -282,6 +378,10 @@ static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) - case APML_CPUID: - ret = rmi_cpuid_read(data, &msg); - break; -+ case APML_MCA_MSR: -+ /* MCAMSR protocol */ -+ ret = rmi_mca_msr_read(data, &msg); -+ break; - default: - return -EINVAL; - } -diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h -index 847a83770ab0..0a841809ca84 100644 ---- a/include/uapi/misc/amd-apml.h -+++ b/include/uapi/misc/amd-apml.h -@@ -7,8 +7,11 @@ - - #include <linux/types.h> - --/* command ID to identify CPUID protocol */ --#define APML_CPUID 0x1000 -+enum apml_protocol { -+ APML_CPUID = 0x1000, -+ APML_MCA_MSR, -+}; -+ - /* These are byte indexes into data_in and data_out arrays */ - #define AMD_SBI_RD_WR_DATA_INDEX 0 - #define AMD_SBI_REG_OFF_INDEX 0 -@@ -24,13 +27,14 @@ struct apml_message { - /* message ids: - * Mailbox Messages: 0x0 ... 0x999 - * APML_CPUID: 0x1000 -+ * APML_MCA_MSR: 0x1001 - */ - __u32 cmd; - - /* - * 8 bit data for reg read, - * 32 bit data in case of mailbox, -- * up to 64 bit in case of cpuid -+ * up to 64 bit in case of cpuid and mca msr - */ - union { - __u64 cpu_msr_out; -@@ -40,8 +44,9 @@ struct apml_message { - - /* - * [0]...[3] mailbox 32bit input -- * cpuid, -- * [4][5] cpuid: thread -+ * cpuid & mca msr, -+ * [4][5] cpuid & mca msr: thread -+ * [4] rmi reg wr: value - * [6] cpuid: ext function & read eax/ebx or ecx/edx - * [7:0] -> bits [7:4] -> ext function & - * bit [0] read eax/ebx or ecx/edx -@@ -53,7 +58,7 @@ struct apml_message { - __u8 reg_in[8]; - } data_in; - /* -- * Status code is returned in case of CPUID access -+ * Status code is returned in case of CPUID/MCA access - * Error code is returned in case of soft mailbox - */ - __u32 fw_ret_code; -@@ -79,6 +84,7 @@ struct apml_message { - * The APML RMI module checks whether the cmd is - * - Mailbox message read/write(0x0~0x999) - * - CPUID read(0x1000) -+ * - MCAMSR read(0x1001) - * - returning "-EFAULT" if none of the above - * "-EPROTOTYPE" error is returned to provide additional error details - */ --- -2.25.1 + MCA registers by passing register address and thread ID to the protocol diff --git a/a/content_digest b/N1/content_digest index 1a2d51e..f6bee90 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -16,233 +16,6 @@ "b\0" "- AMD provides custom protocol to read Machine Check Architecture(MCA)\n" " registers over sideband. The information is accessed for range of\n" - " MCA registers by passing register address and thread ID to the protocol.\n" - " MCA register read command using the register address to access\n" - " Core::X86::Msr::MCG_CAP which determines the number of MCA banks.\n" - " Access is read-only\n" - "\n" - "Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>\n" - "Signed-off-by: Akshay Gupta <akshay.gupta@amd.com>\n" - "---\n" - "Changes since v4:\n" - "- Previously patch 7\n" - "- Address review comment for documentation warning\n" - "\n" - "Changes since v3:\n" - "- Address review comments:\n" - " - update the #define to inline function\n" - " - pack the union inside the structure\n" - "\n" - "Changes since v2:\n" - "- update the MACROS name as per feedback\n" - "\n" - "Changes since v1:\n" - "- bifurcated from previous patch 5\n" - "\n" - " drivers/misc/amd-sbi/rmi-core.c | 100 ++++++++++++++++++++++++++++++++\n" - " include/uapi/misc/amd-apml.h | 18 ++++--\n" - " 2 files changed, 112 insertions(+), 6 deletions(-)\n" - "\n" - "diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c\n" - "index 6fd6e8e579d5..662aa90980fc 100644\n" - "--- a/drivers/misc/amd-sbi/rmi-core.c\n" - "+++ b/drivers/misc/amd-sbi/rmi-core.c\n" - "@@ -30,10 +30,16 @@\n" - " #define CPUID_WR_DATA_LEN\t0x8\n" - " #define CPUID_RD_REG_LEN\t0xa\n" - " #define CPUID_WR_REG_LEN\t0x9\n" - "+/* MSR */\n" - "+#define MSR_RD_REG_LEN\t\t0xa\n" - "+#define MSR_WR_REG_LEN\t\t0x8\n" - "+#define MSR_RD_DATA_LEN\t\t0x8\n" - "+#define MSR_WR_DATA_LEN\t\t0x7\n" - " \n" - " /* CPUID MSR Command Ids */\n" - " #define CPUID_MCA_CMD\t0x73\n" - " #define RD_CPUID_CMD\t0x91\n" - "+#define RD_MCA_CMD\t0x86\n" - " \n" - " /* input for bulk write to CPUID protocol */\n" - " struct cpu_msr_indata {\n" - "@@ -70,6 +76,16 @@ static inline void prepare_cpuid_input_message(struct cpu_msr_indata *input,\n" - " \tinput->ext\t\t= ext_func;\n" - " }\n" - " \n" - "+static inline void prepare_mca_msr_input_message(struct cpu_msr_indata *input,\n" - "+\t\t\t\t\t\t u8 thread_id, u32 data_in)\n" - "+{\n" - "+\tinput->rd_len\t\t= MSR_RD_DATA_LEN;\n" - "+\tinput->wr_len\t\t= MSR_WR_DATA_LEN;\n" - "+\tinput->proto_cmd\t= RD_MCA_CMD;\n" - "+\tinput->thread\t\t= thread_id << 1;\n" - "+\tinput->value\t\t= data_in;\n" - "+}\n" - "+\n" - " static int sbrmi_get_rev(struct sbrmi_data *data)\n" - " {\n" - " \tstruct apml_message msg = { 0 };\n" - "@@ -167,6 +183,86 @@ static int rmi_cpuid_read(struct sbrmi_data *data,\n" - " \treturn ret;\n" - " }\n" - " \n" - "+/* MCA MSR protocol */\n" - "+static int rmi_mca_msr_read(struct sbrmi_data *data,\n" - "+\t\t\t struct apml_message *msg)\n" - "+{\n" - "+\tstruct cpu_msr_outdata output = {0};\n" - "+\tstruct cpu_msr_indata input = {0};\n" - "+\tint ret, val = 0;\n" - "+\tint hw_status;\n" - "+\tu16 thread;\n" - "+\n" - "+\tmutex_lock(&data->lock);\n" - "+\t/* cache the rev value to identify if protocol is supported or not */\n" - "+\tif (!data->rev) {\n" - "+\t\tret = sbrmi_get_rev(data);\n" - "+\t\tif (ret < 0)\n" - "+\t\t\tgoto exit_unlock;\n" - "+\t}\n" - "+\t/* MCA MSR protocol for REV 0x10 is not supported*/\n" - "+\tif (data->rev == 0x10) {\n" - "+\t\tret = -EOPNOTSUPP;\n" - "+\t\tgoto exit_unlock;\n" - "+\t}\n" - "+\n" - "+\tthread = msg->data_in.reg_in[AMD_SBI_THREAD_LOW_INDEX] |\n" - "+\t\t msg->data_in.reg_in[AMD_SBI_THREAD_HI_INDEX] << 8;\n" - "+\n" - "+\t/* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */\n" - "+\tif (thread > 127) {\n" - "+\t\tthread -= 128;\n" - "+\t\tval = 1;\n" - "+\t}\n" - "+\tret = regmap_write(data->regmap, SBRMI_THREAD128CS, val);\n" - "+\tif (ret < 0)\n" - "+\t\tgoto exit_unlock;\n" - "+\n" - "+\tprepare_mca_msr_input_message(&input, thread,\n" - "+\t\t\t\t msg->data_in.mb_in[AMD_SBI_RD_WR_DATA_INDEX]);\n" - "+\n" - "+\tret = regmap_bulk_write(data->regmap, CPUID_MCA_CMD,\n" - "+\t\t\t\t&input, MSR_WR_REG_LEN);\n" - "+\tif (ret < 0)\n" - "+\t\tgoto exit_unlock;\n" - "+\n" - "+\t/*\n" - "+\t * For RMI Rev 0x20, new h/w status bit is introduced. which is used\n" - "+\t * by firmware to indicate completion of commands (0x71, 0x72, 0x73).\n" - "+\t * wait for the status bit to be set by the hardware before\n" - "+\t * reading the data out.\n" - "+\t */\n" - "+\tret = regmap_read_poll_timeout(data->regmap, SBRMI_STATUS, hw_status,\n" - "+\t\t\t\t hw_status & HW_ALERT_MASK, 500, 2000000);\n" - "+\tif (ret)\n" - "+\t\tgoto exit_unlock;\n" - "+\n" - "+\tret = regmap_bulk_read(data->regmap, CPUID_MCA_CMD,\n" - "+\t\t\t &output, MSR_RD_REG_LEN);\n" - "+\tif (ret < 0)\n" - "+\t\tgoto exit_unlock;\n" - "+\n" - "+\tret = regmap_write(data->regmap, SBRMI_STATUS,\n" - "+\t\t\t HW_ALERT_MASK);\n" - "+\tif (ret < 0)\n" - "+\t\tgoto exit_unlock;\n" - "+\n" - "+\tif (output.num_bytes != MSR_RD_REG_LEN - 1) {\n" - "+\t\tret = -EMSGSIZE;\n" - "+\t\tgoto exit_unlock;\n" - "+\t}\n" - "+\tif (output.status) {\n" - "+\t\tret = -EPROTOTYPE;\n" - "+\t\tmsg->fw_ret_code = output.status;\n" - "+\t\tgoto exit_unlock;\n" - "+\t}\n" - "+\tmsg->data_out.cpu_msr_out = output.value;\n" - "+\n" - "+exit_unlock:\n" - "+\tmutex_unlock(&data->lock);\n" - "+\treturn ret;\n" - "+}\n" - "+\n" - " int rmi_mailbox_xfer(struct sbrmi_data *data,\n" - " \t\t struct apml_message *msg)\n" - " {\n" - "@@ -282,6 +378,10 @@ static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)\n" - " \tcase APML_CPUID:\n" - " \t\tret = rmi_cpuid_read(data, &msg);\n" - " \t\tbreak;\n" - "+\tcase APML_MCA_MSR:\n" - "+\t\t/* MCAMSR protocol */\n" - "+\t\tret = rmi_mca_msr_read(data, &msg);\n" - "+\t\tbreak;\n" - " \tdefault:\n" - " \t\treturn -EINVAL;\n" - " \t}\n" - "diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h\n" - "index 847a83770ab0..0a841809ca84 100644\n" - "--- a/include/uapi/misc/amd-apml.h\n" - "+++ b/include/uapi/misc/amd-apml.h\n" - "@@ -7,8 +7,11 @@\n" - " \n" - " #include <linux/types.h>\n" - " \n" - "-/* command ID to identify CPUID protocol */\n" - "-#define APML_CPUID\t0x1000\n" - "+enum apml_protocol {\n" - "+\tAPML_CPUID\t= 0x1000,\n" - "+\tAPML_MCA_MSR,\n" - "+};\n" - "+\n" - " /* These are byte indexes into data_in and data_out arrays */\n" - " #define AMD_SBI_RD_WR_DATA_INDEX\t0\n" - " #define AMD_SBI_REG_OFF_INDEX\t\t0\n" - "@@ -24,13 +27,14 @@ struct apml_message {\n" - " \t/* message ids:\n" - " \t * Mailbox Messages:\t0x0 ... 0x999\n" - " \t * APML_CPUID:\t\t0x1000\n" - "+\t * APML_MCA_MSR:\t0x1001\n" - " \t */\n" - " \t__u32 cmd;\n" - " \n" - " \t/*\n" - " \t * 8 bit data for reg read,\n" - " \t * 32 bit data in case of mailbox,\n" - "-\t * up to 64 bit in case of cpuid\n" - "+\t * up to 64 bit in case of cpuid and mca msr\n" - " \t */\n" - " \tunion {\n" - " \t\t__u64 cpu_msr_out;\n" - "@@ -40,8 +44,9 @@ struct apml_message {\n" - " \n" - " \t/*\n" - " \t * [0]...[3] mailbox 32bit input\n" - "-\t *\t cpuid,\n" - "-\t * [4][5] cpuid: thread\n" - "+\t *\t cpuid & mca msr,\n" - "+\t * [4][5] cpuid & mca msr: thread\n" - "+\t * [4] rmi reg wr: value\n" - " \t * [6] cpuid: ext function & read eax/ebx or ecx/edx\n" - " \t *\t[7:0] -> bits [7:4] -> ext function &\n" - " \t *\tbit [0] read eax/ebx or ecx/edx\n" - "@@ -53,7 +58,7 @@ struct apml_message {\n" - " \t\t__u8 reg_in[8];\n" - " \t} data_in;\n" - " \t/*\n" - "-\t * Status code is returned in case of CPUID access\n" - "+\t * Status code is returned in case of CPUID/MCA access\n" - " \t * Error code is returned in case of soft mailbox\n" - " \t */\n" - " \t__u32 fw_ret_code;\n" - "@@ -79,6 +84,7 @@ struct apml_message {\n" - " * The APML RMI module checks whether the cmd is\n" - " * - Mailbox message read/write(0x0~0x999)\n" - " * - CPUID read(0x1000)\n" - "+ * - MCAMSR read(0x1001)\n" - " * - returning \"-EFAULT\" if none of the above\n" - " * \"-EPROTOTYPE\" error is returned to provide additional error details\n" - " */\n" - "-- \n" - 2.25.1 + MCA registers by passing register address and thread ID to the protocol -5abc3f328137d1171596fbc89eb774e48eda339c6a430114a7a56eb74aff304d +87bbd82ef6d62be9fbf8cd24075b325e90f1471e8d83d5348f0c3dc66c9e6e92
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