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[83.28.83.227]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e530b213asm25243965e9.2.2026.05.06.14.33.37 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 06 May 2026 14:33:38 -0700 (PDT) Date: Wed, 6 May 2026 23:33:32 +0200 From: Michal Pecio To: Jihong Min Cc: Greg Kroah-Hartman , Mathias Nyman , Guenter Roeck , Jonathan Corbet , Shuah Khan , Mario Limonciello , Basavaraj Natikar , linux-usb@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-doc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] hwmon: add initial support for AMD PROM21 xHCI temperature sensor Message-ID: <20260506233332.664f220c.michal.pecio@gmail.com> In-Reply-To: <2e2ea249b30168a2eab62fc110c226a511f21bf2.1778099627.git.hurryman2212@gmail.com> References: <20260506032939.92351-1-hurryman2212@gmail.com> <2e2ea249b30168a2eab62fc110c226a511f21bf2.1778099627.git.hurryman2212@gmail.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, 7 May 2026 05:40:34 +0900, Jihong Min wrote: > AMD PROM21 xHCI controllers expose an 8-bit temperature value I think this commit message and certainly the Kconfig help text should include full name of the chip and perhaps its official marketing names too, so that people better understand what hardware is supported. So: "AMD Promontory 21 chipset" and "AM5 6xx/8xx series chipsets", or whatever they are called by AMD and motherboard vendors. > through a vendor-specific index/data register pair in the xHCI PCI > MMIO BAR region. Add an auxiliary hwmon driver for AMD 1022:43fd > controllers and bind it to the xhci_pci.hwmon auxiliary device > created by xhci-pci. >=20 > The read path verifies the parent PCI function and uses the > initialized xHCI HCD MMIO mapping. The vendor index register is at > byte offset 0x3000 from the xHCI MMIO BAR base and the vendor data > register is at byte offset 0x3008. The driver writes register selector > 0x0001e520 to the index register, reads the raw temperature value from > the low 8 bits of the data register, and restores the previous index > before returning. Expose temp1_input and an xHCI label through hwmon. >=20 > Register the hwmon device under the parent PCI function so userspace > reports it as a PCI adapter, while the auxiliary driver still owns the > hwmon lifetime and unregisters it from the auxiliary remove path. >=20 > No public AMD reference is available for this value. Is there any documentation of the index/data registers themselves? Any potential danger that something else (FW? SMM?) uses them too? > The conversion formula is derived from observed temperature readings: >=20 > temp[C] =3D raw * 0.9066 - 78.624 Could make sense to describe methodology, particularly in case some people would come and question the formula. How was actual chip temperature measured? Was the output compared with any other (Windows?) utilities? People will be comparing these results and possibly trying to draw some conclusions, like OMG Linux runs this chip 8=C2=B0C hotter, should I demand a full refund of my free Ubuntu download????!!!? > The temperature register did not return a valid value while the xHCI > PCI function was suspended in testing. Keep the existing behavior by > default and allow temperature reads to wake the xHCI PCI device. Add an > allow_pm_switch module parameter so users can disable that behavior; > when disabled, reads do not wake the device and return -EAGAIN if it is > suspended. Is such behavior useful? Maybe the driver could just disable runtime PM while it's loaded. >=20 > Document the supported device, register access, conversion formula, > module parameter, sysfs attributes, and sysfs lookup method. >=20 > Assisted-by: Codex:gpt-5.5 > Signed-off-by: Jihong Min