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From: sashiko-bot@kernel.org
To: tze.yee.ng@altera.com
Cc: linux-hwmon@vger.kernel.org
Subject: Re: [PATCH v6 2/2] hwmon: add Altera SoC FPGA hardware monitoring driver
Date: Mon, 20 Jul 2026 03:36:36 +0000	[thread overview]
Message-ID: <20260720033636.A08491F000E9@smtp.kernel.org> (raw)
In-Reply-To: <a686d2c3ef56a3ce28b059621a237259af314032.1784516953.git.tze.yee.ng@altera.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Missing break in async poll loop causes severe kernel log spam and unnecessary blocking on hard errors.
- [High] Synchronous read timeouts leave stale requests in the channel FIFO, causing all subsequent reads to process stale data and return mismatched sensor values.
--

--- Patch [2]: [PATCH v6 2/2] hwmon: add Altera SoC FPGA hardware monitoring driver ---
commit ab6c0c0f95d3890d759e04d9d9aecd151d6406fd
Author: Tze Yee Ng <tze.yee.ng@altera.com>
Subject: hwmon: add Altera SoC FPGA hardware monitoring driver

This commit adds a hardware monitoring driver for Altera SoC FPGA devices using
the Stratix 10 service layer.

> diff --git a/drivers/hwmon/socfpga-hwmon.c b/drivers/hwmon/socfpga-hwmon.c
> new file mode 100644
> index 0000000000000..72418201b65d6
> --- /dev/null
> +++ b/drivers/hwmon/socfpga-hwmon.c
[ ... ]
> +static int socfpga_hwmon_async_read(struct device *dev,
> +				    enum hwmon_sensor_types type,
> +				    struct stratix10_svc_client_msg *msg)
> +{
[ ... ]
> +	ret = -ETIMEDOUT;
> +	while (!time_after(jiffies, deadline)) {
> +		status = stratix10_svc_async_poll(priv->chan, handle, &data);
> +		if (status == -EAGAIN) {
> +			dev_dbg(dev, "Async message is still in progress\n");
> +		} else if (status < 0) {
> +			dev_alert(dev, "Failed to poll async message: %d\n", status);
> +			ret = -ETIMEDOUT;

[Severity: High]
Does this loop need a break statement here when status < 0? 

If stratix10_svc_async_poll() returns a hard error, the code sets 
ret = -ETIMEDOUT but continues to loop for up to 2 seconds. This could
flood the kernel log with dev_alert() messages on every 1ms retry.

> +		} else if (status == 0) {
> +			ret = 0;
> +			break;
> +		}
> +		msleep(HWMON_RETRY_SLEEP_MS);
> +	}
[ ... ]
> +static int socfpga_hwmon_sync_read(struct device *dev,
> +				   enum hwmon_sensor_types type,
> +				   struct stratix10_svc_client_msg *msg)
> +{
[ ... ]
> +	ret = stratix10_svc_send(priv->chan, msg);
> +	if (ret < 0)
> +		goto status_done;
> +
> +	ret = wait_for_completion_timeout(&priv->completion, HWMON_TIMEOUT);
> +	if (!ret) {
> +		dev_err(priv->client.dev, "timeout waiting for SMC call\n");
> +		ret = -ETIMEDOUT;
> +		goto status_done;

[Severity: High]
If a timeout occurs here, could the unfulfilled request remain in the
SVC channel's FIFO?

When the timeout hits, this path calls stratix10_svc_done() which stops the
worker thread, but it doesn't appear to remove the request from chan->svc_fifo.

Would the next sensor read enqueue a new request and receive the stale data
from this timed-out request, permanently desynchronizing all subsequent
sensor readings?

> +	}
> +
> +	ret = priv->last_err;
> +
> +status_done:
> +	stratix10_svc_done(priv->chan);
> +	return ret;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1784516953.git.tze.yee.ng@altera.com?part=2

  reply	other threads:[~2026-07-20  3:36 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-20  3:25 [PATCH v6 0/2] hwmon: add Altera SoC FPGA hardware monitoring support tze.yee.ng
2026-07-20  3:25 ` [PATCH v6 1/2] firmware: stratix10-svc: add async HWMON read commands and register socfpga-hwmon device tze.yee.ng
2026-07-20  3:37   ` sashiko-bot
2026-07-20  4:12     ` Guenter Roeck
2026-07-20 11:04       ` NG, TZE YEE
2026-07-20  3:25 ` [PATCH v6 2/2] hwmon: add Altera SoC FPGA hardware monitoring driver tze.yee.ng
2026-07-20  3:36   ` sashiko-bot [this message]
2026-07-20  4:21     ` Guenter Roeck
2026-07-20 12:44       ` NG, TZE YEE

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