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Mon, 27 Jul 2026 07:41:13 -0700 From: Akhil R To: CC: , , , , , , , , Subject: Re: [PATCH v6 08/12] i3c: dw-i3c-master: Add ACPI core clock frequency quirk Date: Mon, 27 Jul 2026 14:41:12 +0000 Message-ID: <20260727144112.177391-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260721042615.E38721F000E9@smtp.kernel.org> References: <20260721042615.E38721F000E9@smtp.kernel.org> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C1:EE_|DS7PR12MB5837:EE_ X-MS-Office365-Filtering-Correlation-Id: efb03446-76a4-4367-6845-08deebed2ba2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|30052699003|36860700016|23010399003|6133799003|11063799006|56012099006|10067099003|18002099003|22082099003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AUtwfdqjh8rmkTLwWzqrjLjSXKXmCrU2TCnM2EZPBR7T6NJVH1VtfbVVDkGnn+istTwbo3ydGLiLhS1pIydX9OYvIiqGg1qKdOn2Ucxt8plQeR39U3IOLOdEVfXppi2v979K92/3It0ujYuzTbszOeAcvtnCAUow0tq0ljo5W1fOYIDIKt3wAiYTklvI+o2x8eOVDs+zNGD+k4Hc+Nub1UB1fv9Vr03IbHJzPl7YTGwycm/NsaNW96vwwiqNP9Zh2jjgPEMQFYCd7puXHRS2NKxajic09nRNC5kucCjV1Ha1fv5PbpsMTgJPeRVfsr7s28NU39/7xhFNv4k8W3gw1kIg2qKVP1jbhvWgDHEp9UUFdnk3/XRnAkJZ/ll4Kws35wsaljx+y2g/dCYw/CWdrmBHN2/mzbwdaKIc4HkxXvU7jeCF39KeQQTunsbppxQT X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jul 2026 14:41:40.3292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efb03446-76a4-4367-6845-08deebed2ba2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5837 On Tue, 21 Jul 2026 04:26:15 +0000, Sashiko AI review wrote: > commit f3333de342eb1c266eb94909516ea27afe8378d5 > Author: Akhil R > > i3c: dw-i3c-master: Add ACPI core clock frequency quirk > > Some ACPI-enumerated devices like Tegra410 do not expose the controller > core clock through the clk framework. Unlike device tree, ACPI on Arm does > not model clock providers. The hardware is expected to have its clocks > enabled by firmware before the OS takes over. > > > diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c > > index 29030fd9594aa..3ec3ab1c13b4c 100644 > > --- a/drivers/i3c/master/dw-i3c-master.c > > +++ b/drivers/i3c/master/dw-i3c-master.c > > [ ... ] > > > @@ -556,13 +557,33 @@ static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master) > > +static unsigned long dw_i3c_master_get_core_rate(struct dw_i3c_master *master) > > +{ > > + unsigned int core_rate_prop; > > + > > + if (master->core_clk) > > + return clk_get_rate(master->core_clk); > > + > > + if (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) { > > + dev_err(master->dev, "missing core clock\n"); > > + return 0; > > + } > > [Severity: Low] > Is this check reachable? > > During initialization in dw_i3c_common_probe(), if the core clock is missing > and DW_I3C_ACPI_SKIP_CLK_RST is not set, probe immediately aborts with -EINVAL. > > By the time dw_i3c_master_get_core_rate() is executed, it seems guaranteed > that if core_clk is missing, the DW_I3C_ACPI_SKIP_CLK_RST quirk is already > set, making this fallback check dead code. The check is defensive and is harmless. I believe it adds to readability, but can be cleaned up if preferred. > > + > > + if (device_property_read_u32(master->dev, "clock-frequency", &core_rate_prop)) { > > + dev_err(master->dev, "missing clock-frequency property\n"); > > + return 0; > > + } > > + > > + return core_rate_prop; > > +} > > [ ... ] > > > @@ -1573,14 +1594,28 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, > > + if (has_acpi_companion(&pdev->dev)) { > > + quirks = (unsigned long)device_get_match_data(&pdev->dev); > > + } else if (pdev->dev.of_node) { > > [Severity: High] > This isn't a bug introduced by this patch, but since this block was > relocated, I noticed a potential issue for devices using ACPI PRP0001. > > If the device is instantiated via ACPI using the PRP0001 HID, > device_get_match_data() correctly falls back to the OF match table and > returns a pointer to struct dw_i3c_drvdata. > > Does casting this pointer to an unsigned long and assigning it to > master->quirks cause random kernel pointers to be used as a quirk bitmask? > Depending on the kernel layout, this might cause erratic driver behavior such > as missing PM operations. > > + drvdata = device_get_match_data(&pdev->dev); > > + if (drvdata) > > + quirks = drvdata->flags; > > + } > > + master->quirks = quirks; > > [ ... ] > > > @@ -1636,15 +1671,6 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, > > - if (has_acpi_companion(&pdev->dev)) { > > - quirks = (unsigned long)device_get_match_data(&pdev->dev); > > - } else if (pdev->dev.of_node) { > > - drvdata = device_get_match_data(&pdev->dev); > > - if (drvdata) > > - quirks = drvdata->flags; > > - } > > - master->quirks = quirks; > > - > > [Severity: High] > This is a pre-existing issue, but I noticed a potential problem in the device > removal path regarding runtime PM state. > > When the driver is unbound, dw_i3c_common_remove() calls > i3c_master_unregister(), which internally calls dw_i3c_master_bus_cleanup(). > The dw_i3c_master_bus_cleanup() function accesses the DEVICE_CTRL MMIO > register. Because the driver does not wake the device via > pm_runtime_get_sync() before unregistration, the device may be in a > runtime-suspended state with its core clocks disabled. > > Could this cause a fatal bus fault on platforms like ARM due to unclocked MMIO > accesses? Additionally, if the device remains suspended, will the subsequent > devres cleanup attempt to disable the already-disabled clocks, causing a clock > enable counter underflow warning? These are existing issues in the driver. It would be better to address them separately. Best Regards, Akhil