From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B03B6C4332F for ; Thu, 13 Oct 2022 15:52:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229544AbiJMPwZ (ORCPT ); Thu, 13 Oct 2022 11:52:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229587AbiJMPwY (ORCPT ); Thu, 13 Oct 2022 11:52:24 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 106EA37F8F for ; Thu, 13 Oct 2022 08:52:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665676344; x=1697212344; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=HUVBrhgEd1o22OfnnlvDO7MN3MFCs68ewOvy1DJ24/I=; b=PVCWv/LLwjGI44K+nZXpT7k6RH/rsqS3mgM6m5Bl/FTskAfMDavIC9F3 s+f+72utDzdjQ7kQr4/aNnfZhCPZ5iC14qwhJqL9xQRg4mYlvfSzpx8vb NqJeJD0dp2wIEZ+OxVJBrVB/JcXRCj2g20WVk8CFumSum0NjSQs4a3oth NR7WsL4oloxv1L/2IGQ9qt5Z6StPV3AQLXdYrU81VWkvb+dq9yK5fiFL7 j8P4QkxdvSCfFuiNC7uajil/n/iJv3EamwQiBMic1RsVU1nDTnCZstI8k xNLWiVZg0kjcBZuO9nWXeYa/UKfqMWwjiUba+Zsx4AIviyYmWQ9Mfyt2U g==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="367132199" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="367132199" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 08:52:23 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="622209985" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="622209985" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.216.120]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 08:52:23 -0700 Date: Thu, 13 Oct 2022 08:52:23 -0700 Message-ID: <87fsfrsoug.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Andi Shyti Cc: Badal Nilawar , linux-hwmon@vger.kernel.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Riana Tauro Subject: Re: [Intel-gfx] [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support In-Reply-To: References: <20220927055020.3499420-1-badal.nilawar@intel.com> <20220927055020.3499420-3-badal.nilawar@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org On Mon, 03 Oct 2022 13:56:05 -0700, Andi Shyti wrote: Hi Andi, Badal is out for a bit so I am posting this version of the patches. > > Hi Badal, > > [...] > > > static void > > hwm_get_preregistration_info(struct drm_i915_private *i915) > > { > > + struct i915_hwmon *hwmon = i915->hwmon; > > + > > + if (IS_DG1(i915) || IS_DG2(i915)) > > why not GRAPHICS_VER(i915) >= 12 here? Thanks for catching this, because GEN12_RPSTAT1 is indeed available for all Gen12+. It was done this way because the voltage bits of GEN12_RPSTAT1 are only available for DG1/DG2. Anyway in v9 I have changed this to just: /* Available for all Gen12+/dGfx */ hwmon->rg.gt_perf_status = GEN12_RPSTAT1; That is because hwmon is only availbable for dGfx (there's a check in Patch 1). Also, because of this change the 'IS_DG1(i915) || IS_DG2(i915)' check has been moved to hwm_in_is_visible. Thanks. -- Ashutosh > > + hwmon->rg.gt_perf_status = GEN12_RPSTAT1; > > + else > > + hwmon->rg.gt_perf_status = INVALID_MMIO_REG; > > } > > > > void i915_hwmon_register(struct drm_i915_private *i915) > > -- > > 2.25.1