From: sashiko-bot@kernel.org
To: wuliwen <liwen.wu@spacemit.com>
Cc: linux-hwmon@vger.kernel.org
Subject: Re: [PATCH] hwmon: (mr75203) Fix maximum clock divider
Date: Wed, 21 Oct 2026 10:26:43 +0000 [thread overview]
Message-ID: <sashiko-outbox-180097@kernel.org> (raw)
In-Reply-To: <20261021102327.2619070-1-liwen.wu@spacemit.com>
> The MR75203 hardware documentation specifies that the clk_sys to
> clk_ip frequency ratio must be between 2:1 and 512:1. This limit
> is also explicitly documented in the existing pvt_init() comment,
> but CLK_SYS_CYCLES_MAX is incorrectly defined as 514.
>
> As a result, both the divider selection check and the final clamp
> allow values beyond the supported range. At a divider of 514,
> subtracting 2 yields a key of 512, causing the 8-bit CLK_SYNTH
> LO, HI, and HOLD fields to overflow into adjacent bits.
>
> Correct CLK_SYS_CYCLES_MAX to 512 to enforce the documented limit
> and prevent invalid clock synthesizer configurations.
>
> Fixes: 9d823351a337 ("hwmon: Add hardware monitoring driver for Moortec MR75203 PVT controller")
> Signed-off-by: wuliwen <liwen.wu@spacemit.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261021102327.2619070-1-liwen.wu@spacemit.com?part=1
prev parent reply other threads:[~2026-10-21 10:26 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 10:23 [PATCH] hwmon: (mr75203) Fix maximum clock divider wuliwen
2026-10-21 10:26 ` sashiko-bot [this message]
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