From: vdso@mailbox.org
To: Anirudh Rayabharam <anirudh@anirudhrb.com>
Cc: kys@microsoft.com, decui@microsoft.com, haiyangz@microsoft.com,
linux-kernel@vger.kernel.org, longli@microsoft.com,
wei.liu@kernel.org, linux-hyperv@vger.kernel.org
Subject: Re: [PATCH 1/3] hyperv: add definitions for arm64 gpa intercepts
Date: Tue, 16 Dec 2025 07:07:45 -0800 (PST) [thread overview]
Message-ID: <1801063954.177813.1765897665357@app.mailbox.org> (raw)
In-Reply-To: <20251216142030.4095527-2-anirudh@anirudhrb.com>
> On 12/16/2025 6:20 AM Anirudh Rayabharam <anirudh@anirudhrb.com> wrote:
[...]
> +#if IS_ENABLED(CONFIG_ARM64)
> +union hv_arm64_vp_execution_state {
> + u16 as_uint16;
> + struct {
> + u16 cpl:2;
That looks oddly x86(-64)-specific (Current Priviledge Level).
Unless I'm mistaken, CPL doesn't belong here, and the bitfield isn't
used on ARM64. Provided the layout of the struct is correct, the
bitfield can have a better name of `reserved0` or something like that.
> + u16 debug_active:1;
> + u16 interruption_pending:1;
> + u16 vtl:4;
> + u16 virtualization_fault_active:1;
> + u16 reserved:7;
> + } __packed;
next prev parent reply other threads:[~2025-12-16 15:07 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-16 14:20 [PATCH 0/3] Fixes for movable pages Anirudh Rayabharam
2025-12-16 14:20 ` [PATCH 1/3] hyperv: add definitions for arm64 gpa intercepts Anirudh Rayabharam
2025-12-16 15:07 ` vdso [this message]
2025-12-17 5:08 ` Anirudh Rayabharam
2025-12-17 5:46 ` vdso
2025-12-18 20:06 ` Wei Liu
2025-12-16 14:20 ` [PATCH 2/3] mshv: handle gpa intercepts for arm64 Anirudh Rayabharam
2025-12-16 16:11 ` Stanislav Kinsburskii
2025-12-17 5:10 ` Anirudh Rayabharam
2025-12-16 14:20 ` [PATCH 3/3] mshv: release mutex on region invalidation failure Anirudh Rayabharam
2025-12-16 15:14 ` vdso
2025-12-16 16:18 ` Stanislav Kinsburskii
2025-12-18 20:01 ` Wei Liu
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