From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Marc Zyngier <maz@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Wei Huang <wei.huang2@amd.com>,
linux-pci@vger.kernel.org, Peter Zijlstra <peterz@infradead.org>,
Nishanth Menon <nm@ti.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dhruva Gole <d-gole@ti.com>, Tero Kristo <kristo@kernel.org>,
Santosh Shilimkar <ssantosh@kernel.org>,
Logan Gunthorpe <logang@deltatee.com>,
Dave Jiang <dave.jiang@intel.com>, Jon Mason <jdmason@kudzu.us>,
Allen Hubbe <allenbh@gmail.com>,
ntb@lists.linux.dev, Michael Kelley <mhklinux@outlook.com>,
Wei Liu <wei.liu@kernel.org>,
Haiyang Zhang <haiyangz@microsoft.com>,
linux-hyperv@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
"James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>,
"Martin K. Petersen" <martin.petersen@oracle.com>,
linux-scsi@vger.kernel.org,
Jonathan Cameron <Jonathan.Cameron@huwei.com>
Subject: [patch V2 07/10] PCI/MSI: Provide a sane mechanism for TPH
Date: Thu, 13 Mar 2025 14:03:48 +0100 (CET) [thread overview]
Message-ID: <20250313130321.822790423@linutronix.de> (raw)
In-Reply-To: 20250313130212.450198939@linutronix.de
The PCI/TPH driver fiddles with the MSI-X control word of an active
interrupt completely unserialized against concurrent operations issued
from the interrupt core. It also brings the PCI/MSI-X internal cached
control word out of sync.
Provide a function, which has the required serialization and keeps the
control word cache in sync.
Unfortunately this requires to look up and lock the interrupt descriptor,
which should be only done in the interrupt core code. But confining this
particular oddity in the PCI/MSI core is the lesser of all evil. A
interrupt core implementation would require a larger pile of infrastructure
and indirections for dubious value.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Wei Huang <wei.huang2@amd.com>
Cc: linux-pci@vger.kernel.org
---
drivers/pci/msi/msi.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
drivers/pci/pci.h | 9 +++++++++
2 files changed, 56 insertions(+)
--- a/drivers/pci/msi/msi.c
+++ b/drivers/pci/msi/msi.c
@@ -910,6 +910,53 @@ void pci_free_msi_irqs(struct pci_dev *d
}
}
+#ifdef CONFIG_PCIE_TPH
+/**
+ * pci_msix_write_tph_tag - Update the TPH tag for a given MSI-X vector
+ * @pdev: The PCIe device to update
+ * @index: The MSI-X index to update
+ * @tag: The tag to write
+ *
+ * Returns: 0 on success, error code on failure
+ */
+int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag)
+{
+ struct msi_desc *msi_desc;
+ struct irq_desc *irq_desc;
+ unsigned int virq;
+
+ if (!pdev->msix_enabled)
+ return -ENXIO;
+
+ guard(msi_descs_lock)(&pdev->dev);
+ virq = msi_get_virq(&pdev->dev, index);
+ if (!virq)
+ return -ENXIO;
+ /*
+ * This is a horrible hack, but short of implementing a PCI
+ * specific interrupt chip callback and a huge pile of
+ * infrastructure, this is the minor nuissance. It provides the
+ * protection against concurrent operations on this entry and keeps
+ * the control word cache in sync.
+ */
+ irq_desc = irq_to_desc(virq);
+ if (!irq_desc)
+ return -ENXIO;
+
+ guard(raw_spinlock_irq)(&irq_desc->lock);
+ msi_desc = irq_data_get_msi_desc(&irq_desc->irq_data);
+ if (!msi_desc || msi_desc->pci.msi_attrib.is_virtual)
+ return -ENXIO;
+
+ msi_desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_ST;
+ msi_desc->pci.msix_ctrl |= FIELD_PREP(PCI_MSIX_ENTRY_CTRL_ST, tag);
+ pci_msix_write_vector_ctrl(msi_desc, msi_desc->pci.msix_ctrl);
+ /* Flush the write */
+ readl(pci_msix_desc_addr(msi_desc));
+ return 0;
+}
+#endif
+
/* Misc. infrastructure */
struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -989,6 +989,15 @@ int pcim_request_region_exclusive(struct
const char *name);
void pcim_release_region(struct pci_dev *pdev, int bar);
+#ifdef CONFIG_PCI_MSI
+int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag);
+#else
+static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag)
+{
+ return -ENODEV;
+}
+#endif
+
/*
* Config Address for PCI Configuration Mechanism #1
*
next prev parent reply other threads:[~2025-03-13 13:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-13 13:03 [patch V2 00/10] genirq/msi: Spring cleaning Thomas Gleixner
2025-03-13 13:03 ` [patch V2 01/10] cleanup: Provide retain_ptr() Thomas Gleixner
2025-03-13 15:24 ` Jonathan Cameron
2025-03-14 9:37 ` Peter Zijlstra
2025-03-14 14:04 ` Frank Li
2025-03-13 13:03 ` [patch V2 02/10] genirq/msi: Use lock guards for MSI descriptor locking Thomas Gleixner
2025-03-13 15:26 ` Jonathan Cameron
2025-03-13 13:03 ` [patch V2 03/10] soc: ti: ti_sci_inta_msi: Switch MSI descriptor locking to guard() Thomas Gleixner
2025-03-13 13:03 ` [patch V2 04/10] NTB/msi: Switch MSI descriptor locking to lock guard() Thomas Gleixner
2025-03-13 13:03 ` [patch V2 05/10] PCI/MSI: Switch to MSI descriptor locking to guard() Thomas Gleixner
2025-03-13 15:50 ` Jonathan Cameron
2025-03-13 17:55 ` Thomas Gleixner
2025-03-14 9:42 ` Peter Zijlstra
2025-03-13 13:03 ` [patch V2 06/10] PCI: hv: Switch " Thomas Gleixner
2025-03-13 13:03 ` Thomas Gleixner [this message]
2025-03-13 13:03 ` [patch V2 08/10] PCI/TPH: Replace the broken MSI-X control word update Thomas Gleixner
2025-03-13 13:03 ` [patch V2 09/10] scsi: ufs: qcom: Remove the MSI descriptor abuse Thomas Gleixner
2025-03-28 10:00 ` Dan Carpenter
2025-03-28 14:05 ` Thomas Gleixner
2025-03-13 13:03 ` [patch V2 10/10] genirq/msi: Rename msi_[un]lock_descs() Thomas Gleixner
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