From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F39A1E1DF0; Fri, 20 Feb 2026 18:45:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771613122; cv=none; b=GXdeiRLOh0UEsBrTPGJQsnHGiRNd4au+kXx6GqjxAT8kgnuUd3ZTwDFr1E+UwN3k6eBgEA+9FDxB3e9W5QxFOLzxD7HxqKP6fLveftb8wktTmz3fTAI/EkUik2CNrcHzcAULQTF8P8lV3zT8EoZsahJiNb3sMB6y/auHvC/5BbI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771613122; c=relaxed/simple; bh=EEhOFL5oCO1RvjxKnk4k68m/uTYFRt2sJQzQHFz9qDY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=CEHf4HSc4GhIynUNx9z97yu84G5mjcqiqswnmtBZUPIJZiBZnfbHllLjmoHNNRPrSSxj7u8KA4kpxzbIWHLvWNIyRDbN3c40VTyqGp8cY6nAER0ZFpYijBqW6sHmQZi0p5Q+bsQSq+rfDRk5DeIWEaFZQBog7QNCz7jXgXYc0p0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=przVzKPL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="przVzKPL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C74C6C116C6; Fri, 20 Feb 2026 18:45:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771613122; bh=EEhOFL5oCO1RvjxKnk4k68m/uTYFRt2sJQzQHFz9qDY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=przVzKPLUewHWaz/jukYf/6XkNrq6PX37XONBQaQ2WKDqwEpB6aQUDcgY7+zcuiMy Dz6bzjNN7OCvJmrF/6j/gLnklM3XBsaNWqc//aFonUL7vxnaAnRktorYFO8+PKl24u 1VrRNq+dL8MOi7NlkjD4Ux3hs0LlYysWvxCF2AEQO/mFiZYeOzwvCH5KUM5z336OP1 L4Nh57242JS4bf+7WlIu9UB9xaSbxQLAMCM/6P1DxoTtjoMFNK2nVJp0VCNhSQRHmT 1Yvfnfjp+NmUJsmGAskQxWQavgDzdvR9+KamCI6ZNh5cGgB9jQVkJ198detspM8VIp HOrsFFeYGTyvA== Date: Fri, 20 Feb 2026 18:45:20 +0000 From: Wei Liu To: Michael Kelley Cc: Mukesh R , "linux-hyperv@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "kys@microsoft.com" , "haiyangz@microsoft.com" , "wei.liu@kernel.org" , "decui@microsoft.com" , "longli@microsoft.com" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" Subject: Re: [PATCH v2] x86/hyperv: Reserve 3 interrupt vectors used exclusively by mshv Message-ID: <20260220184520.GB3119916@liuwe-devbox-debian-v2.local> References: <20260217231158.1184736-1-mrathor@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-hyperv@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Feb 20, 2026 at 05:14:26PM +0000, Michael Kelley wrote: > From: Mukesh R Sent: Tuesday, February 17, 2026 3:12 PM > > > > MSVC compiler, used to compile the Microsoft Hyper-V hypervisor currently, > > has an assert intrinsic that uses interrupt vector 0x29 to create an > > exception. This will cause hypervisor to then crash and collect core. As > > such, if this interrupt number is assigned to a device by Linux and the > > device generates it, hypervisor will crash. There are two other such > > vectors hard coded in the hypervisor, 0x2C and 0x2D for debug purposes. > > Fortunately, the three vectors are part of the kernel driver space and > > that makes it feasible to reserve them early so they are not assigned > > later. > > > > Signed-off-by: Mukesh Rathor > > --- > > > > v1: Add ifndef CONFIG_X86_FRED (thanks hpa) > > v2: replace ifndef with cpu_feature_enabled() (thanks hpa and tglx) > > > > arch/x86/kernel/cpu/mshyperv.c | 27 +++++++++++++++++++++++++++ > > 1 file changed, 27 insertions(+) > > > > diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c > > index 579fb2c64cfd..88ca127dc6d4 100644 > > --- a/arch/x86/kernel/cpu/mshyperv.c > > +++ b/arch/x86/kernel/cpu/mshyperv.c > > @@ -478,6 +478,28 @@ int hv_get_hypervisor_version(union hv_hypervisor_version_info *info) > > } > > EXPORT_SYMBOL_GPL(hv_get_hypervisor_version); > > > > +/* > > + * Reserve vectors hard coded in the hypervisor. If used outside, the hypervisor > > + * will either crash or hang or attempt to break into debugger. > > + */ > > +static void hv_reserve_irq_vectors(void) > > +{ > > + #define HYPERV_DBG_FASTFAIL_VECTOR 0x29 > > + #define HYPERV_DBG_ASSERT_VECTOR 0x2C > > + #define HYPERV_DBG_SERVICE_VECTOR 0x2D > > + > > + if (cpu_feature_enabled(X86_FEATURE_FRED)) > > + return; > > + > > + if (test_and_set_bit(HYPERV_DBG_ASSERT_VECTOR, system_vectors) || > > + test_and_set_bit(HYPERV_DBG_SERVICE_VECTOR, system_vectors) || > > + test_and_set_bit(HYPERV_DBG_FASTFAIL_VECTOR, system_vectors)) > > + BUG(); > > + > > + pr_info("Hyper-V:reserve vectors: %d %d %d\n", HYPERV_DBG_ASSERT_VECTOR, > > + HYPERV_DBG_SERVICE_VECTOR, HYPERV_DBG_FASTFAIL_VECTOR); > > I'm a little late to the party here, but I've always seen Intel interrupt vectors > displayed as 2-digit hex numbers. This info message is displaying decimal, > which is atypical and will probably be confusing. Noted. The pull request to Linus has been sent. We will change the format in a follow up patch. Wei