From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5527A3ECBC6 for ; Fri, 29 May 2026 14:44:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.202 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780065896; cv=none; b=Az6Oaya3VqY8B4+C2MW+qdk6s9R7z0gcixh6ZibUCSVxQaZwZrS5tHkGvissvMAQpBUP0QC6mBZXhKOpAWncw+uF1Qxpr626NMJ8LZU/HSeI7ju+asuPXpHA1b0Vo/Cvl1CaJ1mtd7mXfYyQDS4/MiNDHwTGgXV3g4fdfrnW1gU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780065896; c=relaxed/simple; bh=DAdh+xk849bonLPf2TMD8IwuAQ4+4Ufk80hi7bNotIQ=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Mn987OBgowkGEMaS5E8+aekzNvBUqLYtWWduaYQBzNOm71S+hWdAiuyng0qh3NBgQPr7Dle8y021UvTEpmoQ6DbALmAy+26lJr8W9Br1PyIMCV9AJMBjUaqbmr3jeSyeMaLfaJFPRFo0FDqmZYAvLMTS1NC6t/aU8TMVmgQuFuQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=jsSHVKod; arc=none smtp.client-ip=209.85.215.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="jsSHVKod" Received: by mail-pg1-f202.google.com with SMTP id 41be03b00d2f7-c828f0f5c23so7201190a12.1 for ; Fri, 29 May 2026 07:44:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1780065894; x=1780670694; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=QToNnoh5SrIptFu//tMv5GaZF9D0Gq2HC3RBnhHkcok=; b=jsSHVKodWqlV+KMQCFwmFHQ62h/VMMnATE9iTQx03+d1rRduAlkN0Z9rIGZW5FrtiJ JTdYkxVVFeS7U3pwGlOG6gnvVBgFruzCvpOjObFr9qvn83H7Y1si1bnU09bY10Q06W2j hhGfAPbHFQKHRzjRem0dm6ssdrPu6VJ1Wc+tOVxC29K3zul8nlEht6sthoKsrLmCyOF8 bKE5SsT+rpTnHGL4qJphI3rZDCfoccfMBQWAR2Pd8JP2yDZo4scOHUJmB1RlwXlwncMZ E4FSygEjGExMqjJWjLoBK3Oe0aqZ/OVOcRI7eH8ppMAuwKVcZzpqB488IQr5SKrrwHZq Codw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780065894; x=1780670694; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=QToNnoh5SrIptFu//tMv5GaZF9D0Gq2HC3RBnhHkcok=; b=dJYq2WAhxdE5WMp8E9X8AL2lrVgMyeZ/eQ0Ka3HHfkpVyZvDAmBsy3n9WiT9MviieO EpyYx6RbmmXNMBwW6i325HfYghVRK8nKX6y/A66Qh/H8BIiYQ/mIjJCtMCciymNV5Vk6 ydyTWqwAPRUhxWn8izDZbcM5tL//1H76dKilOdCvNX80/mX+8m9NLfFUHaXScUNaBrF4 w7Ut0MdRV+b2ebMyXUJqrxpyzPn/p0g93LJj2wAGHKyxwS8mov6M1Z15U3RYumzs+0cE ROHo9/6hcuCCe5JrkTDY6aWgeUnsdfJQJORzYh34HsTeNV/rIOdFXZFllj+ey5Qx2HbG THxA== X-Forwarded-Encrypted: i=1; AFNElJ96JtDX3UB92L1iTaUIM611nzerOkSVjwHubTDrFVCp76QRhILZc4RM51ZvpZ8Y299J9dzl9+KHS1aCZ3M=@vger.kernel.org X-Gm-Message-State: AOJu0YxHDeYm72d+nKaRwmVQLJ1+DT7AoGA7Dnarvg6Th/ZRYFnmZmed JOijCGBt0byicgox+dE5y2LYaQl25p1KIYeClxkSY8cOJl8t3ssAMs3dXqcVF0TYlqlC2DHYym4 2XstpXw== X-Received: from pgce4.prod.google.com ([2002:a05:6a02:1c4:b0:c82:354b:8e38]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:6da0:b0:3b3:bdf5:117e with SMTP id adf61e73a8af0-3b411dd174cmr3909322637.27.1780065893358; Fri, 29 May 2026 07:44:53 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 29 May 2026 07:43:49 -0700 In-Reply-To: <20260529144435.704127-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-hyperv@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260529144435.704127-1-seanjc@google.com> X-Mailer: git-send-email 2.54.0.823.g6e5bcc1fc9-goog Message-ID: <20260529144435.704127-3-seanjc@google.com> Subject: [PATCH v4 02/47] x86/tsc: Add a standalone helpers for getting TSC info from CPUID.0x15 From: Sean Christopherson To: Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, Kiryl Shutsemau , Sean Christopherson , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Ajay Kaher , Alexey Makhalov , Jan Kiszka , Andy Lutomirski , Peter Zijlstra , Juergen Gross , Daniel Lezcano , John Stultz Cc: "H. Peter Anvin" , Rick Edgecombe , Vitaly Kuznetsov , Broadcom internal kernel review list , Boris Ostrovsky , Stephen Boyd , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, xen-devel@lists.xenproject.org, David Woodhouse , Tom Lendacky , Nikunj A Dadhania , David Woodhouse , Michael Kelley , Thomas Gleixner Content-Type: text/plain; charset="UTF-8" Extract retrieval of TSC frequency information from CPUID into standalone helpers so that TDX guest support can reuse the logic. Provide a version that includes the multiplier math as TDX does NOT want to use native_calibrate_tsc()'s fallback logic that derives the TSC frequency based on CPUID.0x16, when the core crystal frequency isn't known. Opportunistically drop native_calibrate_tsc()'s "== 0" and "!= 0" checks in favor of the kernel's preferred style. No functional change intended. Reviewed-by: David Woodhouse Signed-off-by: Sean Christopherson --- arch/x86/include/asm/tsc.h | 8 +++++ arch/x86/kernel/tsc.c | 67 +++++++++++++++++++++++++------------- 2 files changed, 52 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 4f7f09f50552..6cf26e62e9a6 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -83,6 +83,14 @@ static inline cycles_t get_cycles(void) } #define get_cycles get_cycles +struct cpuid_tsc_info { + unsigned int denominator; + unsigned int numerator; + unsigned int crystal_khz; + unsigned int tsc_khz; +}; +extern int __init cpuid_get_tsc_freq(struct cpuid_tsc_info *info); + extern void tsc_early_init(void); extern void tsc_init(void); extern void mark_tsc_unstable(char *reason); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 08cf6625d484..f7f561722efa 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -658,46 +658,67 @@ static unsigned long quick_pit_calibrate(void) return delta; } +static int cpuid_get_tsc_info(struct cpuid_tsc_info *info) +{ + unsigned int ecx_hz, edx; + + memset(info, 0, sizeof(*info)); + + if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) + return -ENOENT; + + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuid(CPUID_LEAF_TSC, &info->denominator, &info->numerator, &ecx_hz, &edx); + + if (!info->denominator || !info->numerator) + return -ENOENT; + + /* + * Note, some CPUs provide the multiplier information, but not the core + * crystal frequency. The multiplier information is still useful for + * such CPUs, as the crystal frequency can be gleaned from CPUID.0x16. + */ + info->crystal_khz = ecx_hz / 1000; + return 0; +} + +int __init cpuid_get_tsc_freq(struct cpuid_tsc_info *info) +{ + if (cpuid_get_tsc_info(info) || !info->crystal_khz) + return -ENOENT; + + info->tsc_khz = info->crystal_khz * info->numerator / info->denominator; + return 0; +} + /** * native_calibrate_tsc - determine TSC frequency * Determine TSC frequency via CPUID, else return 0. */ unsigned long native_calibrate_tsc(void) { - unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; - unsigned int crystal_khz; + struct cpuid_tsc_info info; if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return 0; - if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) + if (cpuid_get_tsc_info(&info)) return 0; - eax_denominator = ebx_numerator = ecx_hz = edx = 0; - - /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ - cpuid(CPUID_LEAF_TSC, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); - - if (ebx_numerator == 0 || eax_denominator == 0) - return 0; - - crystal_khz = ecx_hz / 1000; - /* * Denverton SoCs don't report crystal clock, and also don't support * CPUID_LEAF_FREQ for the calculation below, so hardcode the 25MHz * crystal clock. */ - if (crystal_khz == 0 && - boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT_D) - crystal_khz = 25000; + if (!info.crystal_khz && boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT_D) + info.crystal_khz = 25000; /* * TSC frequency reported directly by CPUID is a "hardware reported" * frequency and is the most accurate one so far we have. This * is considered a known frequency. */ - if (crystal_khz != 0) + if (info.crystal_khz) setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); /* @@ -705,15 +726,15 @@ unsigned long native_calibrate_tsc(void) * clock, but we can easily calculate it to a high degree of accuracy * by considering the crystal ratio and the CPU speed. */ - if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= CPUID_LEAF_FREQ) { + if (!info.crystal_khz && boot_cpu_data.cpuid_level >= CPUID_LEAF_FREQ) { unsigned int eax_base_mhz, ebx, ecx, edx; cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx); - crystal_khz = eax_base_mhz * 1000 * - eax_denominator / ebx_numerator; + info.crystal_khz = eax_base_mhz * 1000 * + info.denominator / info.numerator; } - if (crystal_khz == 0) + if (!info.crystal_khz) return 0; /* @@ -730,10 +751,10 @@ unsigned long native_calibrate_tsc(void) * lapic_timer_period here to avoid having to calibrate the APIC * timer later. */ - lapic_timer_period = crystal_khz * 1000 / HZ; + lapic_timer_period = info.crystal_khz * 1000 / HZ; #endif - return crystal_khz * ebx_numerator / eax_denominator; + return info.crystal_khz * info.numerator / info.denominator; } static unsigned long cpu_khz_from_cpuid(void) -- 2.54.0.823.g6e5bcc1fc9-goog