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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id o5-20020adfeac5000000b0031984b370f2sm14100219wrn.47.2023.09.26.02.26.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Sep 2023 02:26:32 -0700 (PDT) Message-ID: <6e0064bc-65c1-24f5-c29d-c1d1c027e2d3@citrix.com> Date: Tue, 26 Sep 2023 10:26:31 +0100 Precedence: bulk X-Mailing-List: linux-hyperv@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 From: andrew.cooper3@citrix.com Subject: Re: [PATCH v11 05/37] x86/trapnr: Add event type macros to Content-Language: en-GB To: Nikolay Borisov , Xin Li , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, linux-hyperv@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, luto@kernel.org, pbonzini@redhat.com, seanjc@google.com, peterz@infradead.org, jgross@suse.com, ravi.v.shankar@intel.com, mhiramat@kernel.org, jiangshanlai@gmail.com References: <20230923094212.26520-1-xin3.li@intel.com> <20230923094212.26520-6-xin3.li@intel.com> <7acd7bb3-0406-4fd9-8396-835bfd951d87@suse.com> In-Reply-To: <7acd7bb3-0406-4fd9-8396-835bfd951d87@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, NICE_REPLY_A,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On 26/09/2023 9:10 am, Nikolay Borisov wrote: > On 23.09.23 г. 12:41 ч., Xin Li wrote: >> diff --git a/arch/x86/include/asm/trapnr.h >> b/arch/x86/include/asm/trapnr.h >> index f5d2325aa0b7..8d1154cdf787 100644 >> --- a/arch/x86/include/asm/trapnr.h >> +++ b/arch/x86/include/asm/trapnr.h >> @@ -2,6 +2,18 @@ >>   #ifndef _ASM_X86_TRAPNR_H >>   #define _ASM_X86_TRAPNR_H >>   +/* >> + * Event type codes used by FRED, Intel VT-x and AMD SVM >> + */ >> +#define EVENT_TYPE_EXTINT    0    // External interrupt >> +#define EVENT_TYPE_RESERVED    1 >> +#define EVENT_TYPE_NMI        2    // NMI >> +#define EVENT_TYPE_HWEXC    3    // Hardware originated traps, >> exceptions >> +#define EVENT_TYPE_SWINT    4    // INT n >> +#define EVENT_TYPE_PRIV_SWEXC    5    // INT1 >> +#define EVENT_TYPE_SWEXC    6    // INTO, INT3 > > nit: This turned into INTO (Oh) rather than INT0( zero) in v11 Yes, v11 corrected a bug in v10. The INTO instruction is "INT on Overflow".  No zero involved. INT3 is thusly named because it generates vector 3.  Similarly for INT1 although it had the unofficial name ICEBP long before INT1 got documented. If INTO were to have a number, it would need to be 4, but it's behaviour is conditional on the overflow flag, unlike INT3/1 which are unconditional exceptions. ~Andrew