From: Thomas Gleixner <tglx@linutronix.de>
To: Mukesh Rathor <mrathor@linux.microsoft.com>,
linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: kys@microsoft.com, haiyangz@microsoft.com, wei.liu@kernel.org,
decui@microsoft.com, longli@microsoft.com, mingo@redhat.com,
bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org,
hpa@zytor.com
Subject: Re: [PATCH v1] x86/hyperv: Reserve 3 interrupt vectors used exclusively by mshv
Date: Tue, 10 Feb 2026 22:23:14 +0100 [thread overview]
Message-ID: <87bjhw9ttp.ffs@tglx> (raw)
In-Reply-To: <20260102220208.862818-1-mrathor@linux.microsoft.com>
On Fri, Jan 02 2026 at 14:02, Mukesh Rathor wrote:
>
> +#ifndef CONFIG_X86_FRED
This #ifndef is broken. A FRED enabled kernel is no guarantee that the
CPU has FRED. So this has to be unconditional.
> + * Reserve vectors hard coded in the hypervisor. If used outside, the hypervisor
> + * will crash or hang or break into debugger.
> + */
> +static void hv_reserve_irq_vectors(void)
> +{
> + #define HYPERV_DBG_FASTFAIL_VECTOR 0x29
> + #define HYPERV_DBG_ASSERT_VECTOR 0x2C
> + #define HYPERV_DBG_SERVICE_VECTOR 0x2D
As FRED does not need this bit fiddling you want:
if (cpu_feature_enabled(X86_FEATURE_FRED))
return;
right here.
> + if (test_and_set_bit(HYPERV_DBG_ASSERT_VECTOR, system_vectors) ||
> + test_and_set_bit(HYPERV_DBG_SERVICE_VECTOR, system_vectors) ||
> + test_and_set_bit(HYPERV_DBG_FASTFAIL_VECTOR, system_vectors))
> + BUG();
> +
Thanks,
tglx
prev parent reply other threads:[~2026-02-10 21:23 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-02 22:02 [PATCH v1] x86/hyperv: Reserve 3 interrupt vectors used exclusively by mshv Mukesh Rathor
2026-01-15 7:25 ` Wei Liu
2026-01-15 18:16 ` Mukesh R
2026-02-10 19:41 ` H. Peter Anvin
2026-02-10 19:12 ` Mukesh R
2026-02-10 20:33 ` H. Peter Anvin
2026-02-10 21:23 ` Thomas Gleixner [this message]
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