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[91.219.240.2]) by smtp.gmail.com with ESMTPSA id by30-20020a0564021b1e00b004590d4e35cdsm1198745edb.54.2022.10.04.01.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 01:30:11 -0700 (PDT) From: Vitaly Kuznetsov To: Nadav Amit , Alexander Graf , Ajay Kaher Cc: "x86@kernel.org" , "hpa@zytor.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "rostedt@goodmis.org" , Srivatsa Bhat , "srivatsa@csail.mit.edu" , Alexey Makhalov , Vasavi Sirnapalli , "er.ajay.kaher@gmail.com" , "willy@infradead.org" , "linux-hyperv@vger.kernel.org" , "kvm@vger.kernel.org" , "jailhouse-dev@googlegroups.com" , "xen-devel@lists.xenproject.org" , "acrn-dev@lists.projectacrn.org" , "helgaas@kernel.org" , "bhelgaas@google.com" , Thomas Gleixner , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" Subject: Re: [PATCH v2] x86/PCI: Prefer MMIO over PIO on all hypervisor In-Reply-To: <04F550C5-786A-4B8E-9A88-EBFBD8872F16@vmware.com> References: <9FEC6622-780D-41E6-B7CA-8D39EDB2C093@vmware.com> <87zgf3pfd1.fsf@redhat.com> <87tu4l9cfm.fsf@redhat.com> <04F550C5-786A-4B8E-9A88-EBFBD8872F16@vmware.com> Date: Tue, 04 Oct 2022 10:30:10 +0200 Message-ID: <87lepw9ejx.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-hyperv@vger.kernel.org Nadav Amit writes: > On Oct 3, 2022, at 8:03 AM, Vitaly Kuznetsov wrote: > >> Not my but rather PCI maintainer's call but IMHO dropping 'const' is >> better, introducing a new global var is our 'last resort' and should be >> avoided whenever possible. Alternatively, you can add a >> raw_pci_ext_ops_preferred() function checking somethin within 'struct >> hypervisor_x86' but I'm unsure if it's better. >>=20 >> Also, please check Alex' question/suggestion. > > Here is my take (and Ajay knows probably more than me): > > Looking briefly on MCFG, I do not see a clean way of using the ACPI table. > The two options are either to use a reserved field (which who knows, might > be used one day) or some OEM ID. I am also not familiar with > PCI_COMMAND.MEMORY=3D0, so Ajay can hopefully give some answer about that. > > Anyhow, I understand (although not relate) to the objection for a new glo= bal > variable. How about explicitly calling this hardware bug a =E2=80=9Cbug= =E2=80=9D and using > the proper infrastructure? Calling it explicitly a bug may even push whoe= ver > can to resolve it. > > IOW, how about doing something along the lines of (not tested): > Works for me. Going forward, the intention shoud be to also clear the bug on other x86 hypervisors, e.g. we test modern Hyper-V versions and if MMIO works well we clear it, we test modern QEMU/KVM setups and if MMIO works introduce a feature bit somewhere and also clear the bug in the guest when the bit is set. --=20 Vitaly