From: Ingo Molnar <mingo@kernel.org>
To: Xin Li <xin@zytor.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev,
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acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com,
alexander.shishkin@linux.intel.com, jolsa@kernel.org,
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kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com,
Linus Torvalds <torvalds@linux-foundation.org>
Subject: [PATCH] x86/msr: Standardize on 'u32' MSR indices in <asm/msr.h>
Date: Wed, 9 Apr 2025 21:17:02 +0200 [thread overview]
Message-ID: <Z_bHrjUKKWN28TX9@gmail.com> (raw)
In-Reply-To: <c316a6c6-b97c-48b2-9598-d44e2ec72fbc@zytor.com>
* Xin Li <xin@zytor.com> wrote:
> On 4/1/2025 12:52 AM, Ingo Molnar wrote:
> > > Should we rename the *msrl() functions to *msrq() as part of this
> > > overhaul?
> > Yeah, that's a good idea, and because talk is cheap I just implemented
> > this in the tip:WIP.x86/msr branch with a couple of other cleanups in
> > this area (see the shortlog & diffstat below), but the churn is high:
> >
> > 144 files changed, 1034 insertions(+), 1034 deletions(-)
>
> Hi Ingo,
>
> I noticed that you keep the type of MSR index in these patches as
> "unsigned int".
>
> I'm thinking would it be better to standardize it as "u32"?
>
> Because:
> 1) MSR index is placed in ECX to execute MSR instructions, and the
> high-order 32 bits of RCX are ignored on 64-bit.
> 2) MSR index is encoded as a 32-bit immediate in the new immediate form
> MSR instructions.
Makes sense - something like the attached patch?
Thanks,
Ingo
=====================>
From: Ingo Molnar <mingo@kernel.org>
Date: Wed, 9 Apr 2025 21:12:39 +0200
Subject: [PATCH] x86/msr: Standardize on 'u32' MSR indices in <asm/msr.h>
This is the customary type used for hardware ABIs.
Suggested-by: Xin Li <xin@zytor.com>
Suggested-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/msr.h | 29 ++++++++++++++---------------
arch/x86/lib/msr.c | 4 ++--
2 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 4ee9ae734c08..20deb58308e5 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -63,12 +63,12 @@ struct saved_msrs {
DECLARE_TRACEPOINT(read_msr);
DECLARE_TRACEPOINT(write_msr);
DECLARE_TRACEPOINT(rdpmc);
-extern void do_trace_write_msr(unsigned int msr, u64 val, int failed);
-extern void do_trace_read_msr(unsigned int msr, u64 val, int failed);
+extern void do_trace_write_msr(u32 msr, u64 val, int failed);
+extern void do_trace_read_msr(u32 msr, u64 val, int failed);
extern void do_trace_rdpmc(u32 msr, u64 val, int failed);
#else
-static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {}
-static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {}
+static inline void do_trace_write_msr(u32 msr, u64 val, int failed) {}
+static inline void do_trace_read_msr(u32 msr, u64 val, int failed) {}
static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {}
#endif
@@ -79,7 +79,7 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {}
* think of extending them - you will be slapped with a stinking trout or a frozen
* shark will reach you, wherever you are! You've been warned.
*/
-static __always_inline u64 __rdmsr(unsigned int msr)
+static __always_inline u64 __rdmsr(u32 msr)
{
DECLARE_ARGS(val, low, high);
@@ -91,7 +91,7 @@ static __always_inline u64 __rdmsr(unsigned int msr)
return EAX_EDX_VAL(val, low, high);
}
-static __always_inline void __wrmsr(unsigned int msr, u32 low, u32 high)
+static __always_inline void __wrmsr(u32 msr, u32 low, u32 high)
{
asm volatile("1: wrmsr\n"
"2:\n"
@@ -113,7 +113,7 @@ do { \
__wrmsr((msr), (u32)((u64)(val)), \
(u32)((u64)(val) >> 32))
-static inline u64 native_read_msr(unsigned int msr)
+static inline u64 native_read_msr(u32 msr)
{
u64 val;
@@ -125,8 +125,7 @@ static inline u64 native_read_msr(unsigned int msr)
return val;
}
-static inline u64 native_read_msr_safe(unsigned int msr,
- int *err)
+static inline u64 native_read_msr_safe(u32 msr, int *err)
{
DECLARE_ARGS(val, low, high);
@@ -142,7 +141,7 @@ static inline u64 native_read_msr_safe(unsigned int msr,
/* Can be uninlined because referenced by paravirt */
static inline void notrace
-native_write_msr(unsigned int msr, u32 low, u32 high)
+native_write_msr(u32 msr, u32 low, u32 high)
{
__wrmsr(msr, low, high);
@@ -152,7 +151,7 @@ native_write_msr(unsigned int msr, u32 low, u32 high)
/* Can be uninlined because referenced by paravirt */
static inline int notrace
-native_write_msr_safe(unsigned int msr, u32 low, u32 high)
+native_write_msr_safe(u32 msr, u32 low, u32 high)
{
int err;
@@ -251,7 +250,7 @@ do { \
(void)((high) = (u32)(__val >> 32)); \
} while (0)
-static inline void wrmsr(unsigned int msr, u32 low, u32 high)
+static inline void wrmsr(u32 msr, u32 low, u32 high)
{
native_write_msr(msr, low, high);
}
@@ -259,13 +258,13 @@ static inline void wrmsr(unsigned int msr, u32 low, u32 high)
#define rdmsrq(msr, val) \
((val) = native_read_msr((msr)))
-static inline void wrmsrq(unsigned int msr, u64 val)
+static inline void wrmsrq(u32 msr, u64 val)
{
native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
}
/* wrmsr with exception handling */
-static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high)
+static inline int wrmsr_safe(u32 msr, u32 low, u32 high)
{
return native_write_msr_safe(msr, low, high);
}
@@ -280,7 +279,7 @@ static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high)
__err; \
})
-static inline int rdmsrq_safe(unsigned int msr, u64 *p)
+static inline int rdmsrq_safe(u32 msr, u64 *p)
{
int err;
diff --git a/arch/x86/lib/msr.c b/arch/x86/lib/msr.c
index e18925899f13..4ef7c6dcbea6 100644
--- a/arch/x86/lib/msr.c
+++ b/arch/x86/lib/msr.c
@@ -122,14 +122,14 @@ int msr_clear_bit(u32 msr, u8 bit)
EXPORT_SYMBOL_GPL(msr_clear_bit);
#ifdef CONFIG_TRACEPOINTS
-void do_trace_write_msr(unsigned int msr, u64 val, int failed)
+void do_trace_write_msr(u32 msr, u64 val, int failed)
{
trace_write_msr(msr, val, failed);
}
EXPORT_SYMBOL(do_trace_write_msr);
EXPORT_TRACEPOINT_SYMBOL(write_msr);
-void do_trace_read_msr(unsigned int msr, u64 val, int failed)
+void do_trace_read_msr(u32 msr, u64 val, int failed)
{
trace_read_msr(msr, val, failed);
}
next prev parent reply other threads:[~2025-04-09 19:17 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-31 8:22 [RFC PATCH v1 00/15] MSR refactor with new MSR instructions support Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 01/15] x86/msr: Replace __wrmsr() with native_wrmsrl() Xin Li (Intel)
2025-03-31 10:17 ` Ingo Molnar
2025-03-31 20:32 ` H. Peter Anvin
2025-04-01 5:53 ` Xin Li
2025-04-02 15:41 ` Dave Hansen
2025-04-02 15:56 ` H. Peter Anvin
2025-04-09 19:53 ` Ingo Molnar
2025-04-09 19:56 ` Dave Hansen
2025-04-09 20:11 ` Ingo Molnar
2025-04-01 7:52 ` Ingo Molnar
2025-04-02 3:45 ` Xin Li
2025-04-02 4:10 ` Ingo Molnar
2025-04-02 4:57 ` Xin Li
2025-04-08 17:34 ` Xin Li
2025-04-03 5:09 ` Xin Li
2025-04-03 6:01 ` H. Peter Anvin
2025-04-09 19:17 ` Ingo Molnar [this message]
2025-03-31 21:45 ` Andrew Cooper
2025-04-01 5:13 ` H. Peter Anvin
2025-04-01 5:29 ` Xin Li
2025-04-03 7:13 ` Xin Li
2025-03-31 8:22 ` [RFC PATCH v1 02/15] x86/msr: Replace __rdmsr() with native_rdmsrl() Xin Li (Intel)
2025-03-31 10:26 ` Ingo Molnar
2025-03-31 8:22 ` [RFC PATCH v1 03/15] x86/msr: Simplify pmu_msr_{read,write}() Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 04/15] x86/msr: Let pv_cpu_ops.write_msr{_safe}() take an u64 instead of two u32 Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 05/15] x86/msr: Replace wrmsr(msr, low, 0) with wrmsrl(msr, value) Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 06/15] x86/msr: Remove MSR write APIs that take the MSR value in two u32 arguments Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 07/15] x86/msr: Remove pmu_msr_{read,write}() Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 08/15] x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 09/15] x86/opcode: Add immediate form MSR instructions to x86-opcode-map Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 10/15] KVM: VMX: Use WRMSRNS or its immediate form when available Xin Li (Intel)
2025-03-31 20:27 ` Konrad Rzeszutek Wilk
2025-03-31 20:38 ` Borislav Petkov
2025-03-31 20:41 ` Andrew Cooper
2025-03-31 20:55 ` H. Peter Anvin
2025-03-31 20:45 ` H. Peter Anvin
2025-04-10 23:24 ` Sean Christopherson
2025-04-11 16:18 ` Xin Li
2025-04-11 20:50 ` H. Peter Anvin
2025-04-12 4:28 ` Xin Li
2025-04-11 21:12 ` Jim Mattson
2025-04-12 4:32 ` Xin Li
2025-04-12 23:10 ` H. Peter Anvin
2025-04-14 17:48 ` Xin Li
2025-04-15 6:56 ` H. Peter Anvin
2025-04-15 17:06 ` Xin Li
2025-04-15 17:07 ` H. Peter Anvin
2025-03-31 8:22 ` [RFC PATCH v1 11/15] x86/extable: Implement EX_TYPE_FUNC_REWIND Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 12/15] x86/msr: Use the alternatives mechanism to write MSR Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 13/15] x86/msr: Use the alternatives mechanism to read MSR Xin Li (Intel)
2025-04-14 17:13 ` Francesco Lavra
2025-04-17 11:10 ` Xin Li
2025-03-31 8:22 ` [RFC PATCH v1 14/15] x86/extable: Add support for the immediate form MSR instructions Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 15/15] x86/msr: Move the ARGS macros after the MSR read/write APIs Xin Li (Intel)
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