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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id v26-20020a1cf71a000000b003fe1630a8f0sm5015544wmh.24.2023.09.14.07.22.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Sep 2023 07:22:28 -0700 (PDT) Message-ID: Date: Thu, 14 Sep 2023 15:22:27 +0100 Precedence: bulk X-Mailing-List: linux-hyperv@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 From: andrew.cooper3@citrix.com Subject: Re: [PATCH v10 05/38] x86/trapnr: Add event type macros to Content-Language: en-GB To: Xin Li , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, linux-hyperv@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, luto@kernel.org, pbonzini@redhat.com, seanjc@google.com, peterz@infradead.org, jgross@suse.com, ravi.v.shankar@intel.com, mhiramat@kernel.org, jiangshanlai@gmail.com References: <20230914044805.301390-1-xin3.li@intel.com> <20230914044805.301390-6-xin3.li@intel.com> In-Reply-To: <20230914044805.301390-6-xin3.li@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 14/09/2023 5:47 am, Xin Li wrote: > Intel VT-x classifies events into eight different types, which is > inherited by FRED for event identification. As such, event type > becomes a common x86 concept, and should be defined in a common x86 > header. > > Add event type macros to , and use it in . > > Suggested-by: H. Peter Anvin (Intel) > Tested-by: Shan Kang > Signed-off-by: Xin Li > --- > arch/x86/include/asm/trapnr.h | 12 ++++++++++++ > arch/x86/include/asm/vmx.h | 17 +++++++++-------- > 2 files changed, 21 insertions(+), 8 deletions(-) > > diff --git a/arch/x86/include/asm/trapnr.h b/arch/x86/include/asm/trapnr.h > index f5d2325aa0b7..ab7e4c9d666f 100644 > --- a/arch/x86/include/asm/trapnr.h > +++ b/arch/x86/include/asm/trapnr.h > @@ -2,6 +2,18 @@ > #ifndef _ASM_X86_TRAPNR_H > #define _ASM_X86_TRAPNR_H > > +/* > + * Event type codes used by both FRED and Intel VT-x And AMD SVM.  This enumeration has never been unique to just VT-x. > + */ > +#define EVENT_TYPE_EXTINT 0 // External interrupt > +#define EVENT_TYPE_RESERVED 1 > +#define EVENT_TYPE_NMI 2 // NMI > +#define EVENT_TYPE_HWEXC 3 // Hardware originated traps, exceptions > +#define EVENT_TYPE_SWINT 4 // INT n > +#define EVENT_TYPE_PRIV_SWEXC 5 // INT1 > +#define EVENT_TYPE_SWEXC 6 // INT0, INT3 Typo.  into, not int0  (the difference shows up more clearly in lower case.) > diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h > index 0e73616b82f3..c84acfefcd31 100644 > --- a/arch/x86/include/asm/vmx.h > +++ b/arch/x86/include/asm/vmx.h > @@ -374,14 +375,14 @@ enum vmcs_field { > #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK > #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK > > -#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ > -#define INTR_TYPE_RESERVED (1 << 8) /* reserved */ > -#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ > -#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ > -#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ > -#define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */ > -#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ > -#define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ > +#define INTR_TYPE_EXT_INTR (EVENT_TYPE_EXTINT << 8) /* external interrupt */ > +#define INTR_TYPE_RESERVED (EVENT_TYPE_RESERVED << 8) /* reserved */ > +#define INTR_TYPE_NMI_INTR (EVENT_TYPE_NMI << 8) /* NMI */ > +#define INTR_TYPE_HARD_EXCEPTION (EVENT_TYPE_HWEXC << 8) /* processor exception */ > +#define INTR_TYPE_SOFT_INTR (EVENT_TYPE_SWINT << 8) /* software interrupt */ > +#define INTR_TYPE_PRIV_SW_EXCEPTION (EVENT_TYPE_PRIV_SWEXC << 8) /* ICE breakpoint - undocumented */ ICEBP/INT1 is no longer undocumented. ~Andrew