From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
kevin.z.m.zh-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
sunny-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org,
shuge-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org,
zhuzhenhua-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org,
duanmintao-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Subject: [PATCH 2/5] i2c: mv64xxx: Add support for the Allwinner A31 I2C driver
Date: Thu, 9 Jan 2014 18:20:00 +0100 [thread overview]
Message-ID: <1389288003-23187-3-git-send-email-maxime.ripard@free-electrons.com> (raw)
In-Reply-To: <1389288003-23187-1-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
The Allwinner A31 I2C controller is almost identical to the one used in the
other Allwinner SoCs, except for the fact that it needs to clear the interrupt
by setting the INT_FLAGS bit in the control register, instead of clearing it.
Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/i2c/busses/i2c-mv64xxx.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index d4e2f32..a2f6173 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -150,6 +150,7 @@ struct mv64xxx_i2c_data {
bool offload_enabled;
/* 5us delay in order to avoid repeated start timing violation */
bool errata_delay;
+ bool irq_clear_inverted;
};
static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
@@ -567,6 +568,11 @@ mv64xxx_i2c_intr(int irq, void *dev_id)
status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
mv64xxx_i2c_fsm(drv_data, status);
mv64xxx_i2c_do_action(drv_data);
+
+ if (drv_data->irq_clear_inverted)
+ writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
+ drv_data->reg_base + drv_data->reg_offsets.control);
+
rc = IRQ_HANDLED;
}
spin_unlock_irqrestore(&drv_data->lock, flags);
@@ -691,6 +697,7 @@ static const struct i2c_algorithm mv64xxx_i2c_algo = {
*/
static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
{ .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i},
+ { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
{ .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
{ .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
{}
@@ -789,6 +796,9 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
drv_data->errata_delay = true;
}
+ if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
+ drv_data->irq_clear_inverted = true;
+
out:
return rc;
#endif
--
1.8.4.2
next prev parent reply other threads:[~2014-01-09 17:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-09 17:19 [PATCH 0/5] ARM: sun6i: Add support for the A31 I2C controller Maxime Ripard
[not found] ` <1389288003-23187-1-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-01-09 17:19 ` [PATCH 1/5] i2c: mv64xxx: Add reset deassert call Maxime Ripard
[not found] ` <1389288003-23187-2-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-01-10 5:48 ` Chen-Yu Tsai
[not found] ` <CAGb2v6663ARKwmJ4Ypzi=m-J7UMvUFRq1=qLbqgQ0vrN_gC18w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-01-10 17:24 ` Maxime Ripard
2014-01-09 17:20 ` Maxime Ripard [this message]
2014-01-09 17:20 ` [PATCH 3/5] ARM: sun6i: Enable the I2C controllers Maxime Ripard
2014-01-09 17:20 ` [PATCH 4/5] ARM: sun6i: Enable the I2C muxing options Maxime Ripard
2014-01-09 17:20 ` [PATCH 5/5] ARM: sun6i: colombus: Enable the I2C controllers Maxime Ripard
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