[PATCH v2 1/4] i2c: designware-pci: remove Moorestown support

[PATCH v2 1/4] i2c: designware-pci: remove Moorestown support

[Andy Shevchenko]

The Moorestown support bits were removed few years ago. This is a follow up to
that changes.

Suggested-by: David Cohen <david.a.cohen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 29 -----------------------------
 1 file changed, 29 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index acb40f9..5c6fca7 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -40,10 +40,6 @@
 #define DRIVER_NAME "i2c-designware-pci"
 
 enum dw_pci_ctl_id_t {
-	moorestown_0,
-	moorestown_1,
-	moorestown_2,
-
 	medfield_0,
 	medfield_1,
 	medfield_2,
@@ -102,27 +98,6 @@ static struct dw_scl_sda_cfg hsw_config = {
 };
 
 static struct  dw_pci_controller  dw_pci_controllers[] = {
-	[moorestown_0] = {
-		.bus_num     = 0,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[moorestown_1] = {
-		.bus_num     = 1,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[moorestown_2] = {
-		.bus_num     = 2,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
 	[medfield_0] = {
 		.bus_num     = 0,
 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
@@ -325,10 +300,6 @@ static void i2c_dw_pci_remove(struct pci_dev *pdev)
 MODULE_ALIAS("i2c_designware-pci");
 
 static const struct pci_device_id i2_designware_pci_ids[] = {
-	/* Moorestown */
-	{ PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
-	{ PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
-	{ PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
 	/* Medfield */
 	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
 	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
-- 
2.1.4

[PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[Andy Shevchenko]

There is no need to duplicate same data for each controller. If we need
specific stuff for a certain controller in the future we may add it later. The
patch leaves one controller per platform.

Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 63 ++++++------------------------
 1 file changed, 11 insertions(+), 52 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 5c6fca7..435a8ec 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -40,13 +40,7 @@
 #define DRIVER_NAME "i2c-designware-pci"
 
 enum dw_pci_ctl_id_t {
-	medfield_0,
-	medfield_1,
-	medfield_2,
-	medfield_3,
-	medfield_4,
-	medfield_5,
-
+	medfield,
 	baytrail,
 	haswell,
 };
@@ -98,47 +92,12 @@ static struct dw_scl_sda_cfg hsw_config = {
 };
 
 static struct  dw_pci_controller  dw_pci_controllers[] = {
-	[medfield_0] = {
-		.bus_num     = 0,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_1] = {
-		.bus_num     = 1,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_2] = {
-		.bus_num     = 2,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_3] = {
-		.bus_num     = 3,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_4] = {
-		.bus_num     = 4,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-		.tx_fifo_depth = 32,
-		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
-	},
-	[medfield_5] = {
-		.bus_num     = 5,
-		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
+	[medfield] = {
+		.bus_num = -1,
+		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 		.tx_fifo_depth = 32,
 		.rx_fifo_depth = 32,
-		.clk_khz      = 25000,
+		.clk_khz = 25000,
 	},
 	[baytrail] = {
 		.bus_num = -1,
@@ -301,12 +260,12 @@ MODULE_ALIAS("i2c_designware-pci");
 
 static const struct pci_device_id i2_designware_pci_ids[] = {
 	/* Medfield */
-	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
-	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
-	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
-	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
-	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
-	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
+	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
+	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
+	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082c), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082d), medfield },
+	{ PCI_VDEVICE(INTEL, 0x082e), medfield },
 	/* Baytrail */
 	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
-- 
2.1.4

[PATCH v2 3/4] i2c: designware-pci: no need to provide clk_khz

[Andy Shevchenko]

The clk_khz field makes sense only if SS counters are not provided. Since we
provide them for Haswell and Baytrail explicitly we may omit the clk_khz
parameter.

Reviewed-by: Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 435a8ec..cddb20d 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -104,7 +104,6 @@ static struct  dw_pci_controller  dw_pci_controllers[] = {
 		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 		.tx_fifo_depth = 32,
 		.rx_fifo_depth = 32,
-		.clk_khz = 100000,
 		.functionality = I2C_FUNC_10BIT_ADDR,
 		.scl_sda_cfg = &byt_config,
 	},
@@ -113,7 +112,6 @@ static struct  dw_pci_controller  dw_pci_controllers[] = {
 		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 		.tx_fifo_depth = 32,
 		.rx_fifo_depth = 32,
-		.clk_khz = 100000,
 		.functionality = I2C_FUNC_10BIT_ADDR,
 		.scl_sda_cfg = &hsw_config,
 	},
-- 
2.1.4

[PATCH v2 4/4] i2c: designware-pci: update Intel copyright line

[Andy Shevchenko]

While here, fix few indentations issues across the code. There is no functional
change.

Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/i2c/busses/i2c-designware-pcidrv.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index cddb20d..e7972d8 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -6,7 +6,7 @@
  * Copyright (C) 2006 Texas Instruments.
  * Copyright (C) 2007 MontaVista Software Inc.
  * Copyright (C) 2009 Provigent Ltd.
- * Copyright (C) 2011 Intel corporation.
+ * Copyright (C) 2011, 2015 Intel Corporation.
  *
  * ----------------------------------------------------------------------------
  *
@@ -91,7 +91,7 @@ static struct dw_scl_sda_cfg hsw_config = {
 	.sda_hold = 0x9,
 };
 
-static struct  dw_pci_controller  dw_pci_controllers[] = {
+static struct dw_pci_controller dw_pci_controllers[] = {
 	[medfield] = {
 		.bus_num = -1,
 		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
@@ -191,7 +191,7 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
 	dev->functionality = controller->functionality |
 				DW_DEFAULT_FUNCTIONALITY;
 
-	dev->master_cfg =  controller->bus_cfg;
+	dev->master_cfg = controller->bus_cfg;
 	if (controller->scl_sda_cfg) {
 		cfg = controller->scl_sda_cfg;
 		dev->ss_hcnt = cfg->ss_hcnt;
@@ -276,7 +276,7 @@ static const struct pci_device_id i2_designware_pci_ids[] = {
 	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
 	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
 	/* Braswell / Cherrytrail */
-	{ PCI_VDEVICE(INTEL, 0x22C1), baytrail,},
+	{ PCI_VDEVICE(INTEL, 0x22C1), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x22C2), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x22C3), baytrail },
 	{ PCI_VDEVICE(INTEL, 0x22C4), baytrail },
-- 
2.1.4

Re: [PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[Wolfram Sang]

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On Fri, Jan 23, 2015 at 01:54:03PM +0200, Andy Shevchenko wrote:
> There is no need to duplicate same data for each controller. If we need
> specific stuff for a certain controller in the future we may add it later. The
> patch leaves one controller per platform.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> ---
>  drivers/i2c/busses/i2c-designware-pcidrv.c | 63 ++++++------------------------
>  1 file changed, 11 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> index 5c6fca7..435a8ec 100644
> --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> @@ -40,13 +40,7 @@
>  #define DRIVER_NAME "i2c-designware-pci"
>  
>  enum dw_pci_ctl_id_t {
> -	medfield_0,
> -	medfield_1,
> -	medfield_2,
> -	medfield_3,
> -	medfield_4,
> -	medfield_5,
> -
> +	medfield,
>  	baytrail,
>  	haswell,
>  };
> @@ -98,47 +92,12 @@ static struct dw_scl_sda_cfg hsw_config = {
>  };
>  
>  static struct  dw_pci_controller  dw_pci_controllers[] = {
> -	[medfield_0] = {
> -		.bus_num     = 0,

Wasn't that bus_num used to ensure stable bus numbers? Adding Mika.

> -		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
> -		.tx_fifo_depth = 32,
> -		.rx_fifo_depth = 32,
> -		.clk_khz      = 25000,
> -	},
> -	[medfield_1] = {
> -		.bus_num     = 1,
> -		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
> -		.tx_fifo_depth = 32,
> -		.rx_fifo_depth = 32,
> -		.clk_khz      = 25000,
> -	},
> -	[medfield_2] = {
> -		.bus_num     = 2,
> -		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
> -		.tx_fifo_depth = 32,
> -		.rx_fifo_depth = 32,
> -		.clk_khz      = 25000,
> -	},
> -	[medfield_3] = {
> -		.bus_num     = 3,
> -		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
> -		.tx_fifo_depth = 32,
> -		.rx_fifo_depth = 32,
> -		.clk_khz      = 25000,
> -	},
> -	[medfield_4] = {
> -		.bus_num     = 4,
> -		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
> -		.tx_fifo_depth = 32,
> -		.rx_fifo_depth = 32,
> -		.clk_khz      = 25000,
> -	},
> -	[medfield_5] = {
> -		.bus_num     = 5,
> -		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
> +	[medfield] = {
> +		.bus_num = -1,
> +		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
>  		.tx_fifo_depth = 32,
>  		.rx_fifo_depth = 32,
> -		.clk_khz      = 25000,
> +		.clk_khz = 25000,
>  	},
>  	[baytrail] = {
>  		.bus_num = -1,
> @@ -301,12 +260,12 @@ MODULE_ALIAS("i2c_designware-pci");
>  
>  static const struct pci_device_id i2_designware_pci_ids[] = {
>  	/* Medfield */
> -	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
> -	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
> -	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
> -	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
> -	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
> -	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
> +	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
> +	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
> +	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
> +	{ PCI_VDEVICE(INTEL, 0x082c), medfield },
> +	{ PCI_VDEVICE(INTEL, 0x082d), medfield },
> +	{ PCI_VDEVICE(INTEL, 0x082e), medfield },
>  	/* Baytrail */
>  	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
>  	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
> -- 
> 2.1.4
> 

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Re: [PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[Mika Westerberg]

On Fri, Jan 23, 2015 at 01:41:55PM +0100, Wolfram Sang wrote:
> On Fri, Jan 23, 2015 at 01:54:03PM +0200, Andy Shevchenko wrote:
> > There is no need to duplicate same data for each controller. If we need
> > specific stuff for a certain controller in the future we may add it later. The
> > patch leaves one controller per platform.
> > 
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> > ---
> >  drivers/i2c/busses/i2c-designware-pcidrv.c | 63 ++++++------------------------
> >  1 file changed, 11 insertions(+), 52 deletions(-)
> > 
> > diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > index 5c6fca7..435a8ec 100644
> > --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > @@ -40,13 +40,7 @@
> >  #define DRIVER_NAME "i2c-designware-pci"
> >  
> >  enum dw_pci_ctl_id_t {
> > -	medfield_0,
> > -	medfield_1,
> > -	medfield_2,
> > -	medfield_3,
> > -	medfield_4,
> > -	medfield_5,
> > -
> > +	medfield,
> >  	baytrail,
> >  	haswell,
> >  };
> > @@ -98,47 +92,12 @@ static struct dw_scl_sda_cfg hsw_config = {
> >  };
> >  
> >  static struct  dw_pci_controller  dw_pci_controllers[] = {
> > -	[medfield_0] = {
> > -		.bus_num     = 0,
> 
> Wasn't that bus_num used to ensure stable bus numbers? Adding Mika.

That's right.

However, I don't think anybody really uses Medfield outside Intel so in
that sense this patch should not break anything.

Re: [PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[Andy Shevchenko]

On Fri, 2015-01-23 at 14:48 +0200, Mika Westerberg wrote:
> On Fri, Jan 23, 2015 at 01:41:55PM +0100, Wolfram Sang wrote:
> > On Fri, Jan 23, 2015 at 01:54:03PM +0200, Andy Shevchenko wrote:
> > > There is no need to duplicate same data for each controller. If we need
> > > specific stuff for a certain controller in the future we may add it later. The
> > > patch leaves one controller per platform.
> > > 
> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> > > ---
> > >  drivers/i2c/busses/i2c-designware-pcidrv.c | 63 ++++++------------------------
> > >  1 file changed, 11 insertions(+), 52 deletions(-)
> > > 
> > > diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > index 5c6fca7..435a8ec 100644
> > > --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > @@ -40,13 +40,7 @@
> > >  #define DRIVER_NAME "i2c-designware-pci"
> > >  
> > >  enum dw_pci_ctl_id_t {
> > > -	medfield_0,
> > > -	medfield_1,
> > > -	medfield_2,
> > > -	medfield_3,
> > > -	medfield_4,
> > > -	medfield_5,
> > > -
> > > +	medfield,
> > >  	baytrail,
> > >  	haswell,
> > >  };
> > > @@ -98,47 +92,12 @@ static struct dw_scl_sda_cfg hsw_config = {
> > >  };
> > >  
> > >  static struct  dw_pci_controller  dw_pci_controllers[] = {
> > > -	[medfield_0] = {
> > > -		.bus_num     = 0,
> > 
> > Wasn't that bus_num used to ensure stable bus numbers? Adding Mika.
> 
> That's right.
> 
> However, I don't think anybody really uses Medfield outside Intel so in
> that sense this patch should not break anything.

I think better to ask David who is closer to that Intel MID area.

AFAIU, technically due to fake PCI bus on Medfield even with automatic
bus number you will get stable assignment, though it might be changed
once from the original version.

-- 
Andy Shevchenko <andriy.shevchenko-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Intel Finland Oy

Re: [PATCH v2 1/4] i2c: designware-pci: remove Moorestown support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 491 bytes --]

On Fri, Jan 23, 2015 at 01:54:02PM +0200, Andy Shevchenko wrote:
> The Moorestown support bits were removed few years ago. This is a follow up to
> that changes.
> 
> Suggested-by: David Cohen <david.a.cohen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

Applied to for-next, thanks!

Please describe the changes since last version, either below the patch
description or in a cover-letter.


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Re: [PATCH v2 3/4] i2c: designware-pci: no need to provide clk_khz

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 454 bytes --]

On Fri, Jan 23, 2015 at 01:54:04PM +0200, Andy Shevchenko wrote:
> The clk_khz field makes sense only if SS counters are not provided. Since we
> provide them for Haswell and Baytrail explicitly we may omit the clk_khz
> parameter.
> 
> Reviewed-by: Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

Applied to for-next, thanks!


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Re: [PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[Wolfram Sang]

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On Fri, Jan 23, 2015 at 03:04:06PM +0200, Andy Shevchenko wrote:
> On Fri, 2015-01-23 at 14:48 +0200, Mika Westerberg wrote:
> > On Fri, Jan 23, 2015 at 01:41:55PM +0100, Wolfram Sang wrote:
> > > On Fri, Jan 23, 2015 at 01:54:03PM +0200, Andy Shevchenko wrote:
> > > > There is no need to duplicate same data for each controller. If we need
> > > > specific stuff for a certain controller in the future we may add it later. The
> > > > patch leaves one controller per platform.
> > > > 
> > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> > > > ---
> > > >  drivers/i2c/busses/i2c-designware-pcidrv.c | 63 ++++++------------------------
> > > >  1 file changed, 11 insertions(+), 52 deletions(-)
> > > > 
> > > > diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > index 5c6fca7..435a8ec 100644
> > > > --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > @@ -40,13 +40,7 @@
> > > >  #define DRIVER_NAME "i2c-designware-pci"
> > > >  
> > > >  enum dw_pci_ctl_id_t {
> > > > -	medfield_0,
> > > > -	medfield_1,
> > > > -	medfield_2,
> > > > -	medfield_3,
> > > > -	medfield_4,
> > > > -	medfield_5,
> > > > -
> > > > +	medfield,
> > > >  	baytrail,
> > > >  	haswell,
> > > >  };
> > > > @@ -98,47 +92,12 @@ static struct dw_scl_sda_cfg hsw_config = {
> > > >  };
> > > >  
> > > >  static struct  dw_pci_controller  dw_pci_controllers[] = {
> > > > -	[medfield_0] = {
> > > > -		.bus_num     = 0,
> > > 
> > > Wasn't that bus_num used to ensure stable bus numbers? Adding Mika.
> > 
> > That's right.
> > 
> > However, I don't think anybody really uses Medfield outside Intel so in
> > that sense this patch should not break anything.
> 
> I think better to ask David who is closer to that Intel MID area.

OK, waiting for a reply from him here.


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Re: [PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[Wolfram Sang]

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On Sat, Jan 24, 2015 at 05:19:14AM +0100, Wolfram Sang wrote:
> On Fri, Jan 23, 2015 at 03:04:06PM +0200, Andy Shevchenko wrote:
> > On Fri, 2015-01-23 at 14:48 +0200, Mika Westerberg wrote:
> > > On Fri, Jan 23, 2015 at 01:41:55PM +0100, Wolfram Sang wrote:
> > > > On Fri, Jan 23, 2015 at 01:54:03PM +0200, Andy Shevchenko wrote:
> > > > > There is no need to duplicate same data for each controller. If we need
> > > > > specific stuff for a certain controller in the future we may add it later. The
> > > > > patch leaves one controller per platform.
> > > > > 
> > > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> > > > > ---
> > > > >  drivers/i2c/busses/i2c-designware-pcidrv.c | 63 ++++++------------------------
> > > > >  1 file changed, 11 insertions(+), 52 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > index 5c6fca7..435a8ec 100644
> > > > > --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > @@ -40,13 +40,7 @@
> > > > >  #define DRIVER_NAME "i2c-designware-pci"
> > > > >  
> > > > >  enum dw_pci_ctl_id_t {
> > > > > -	medfield_0,
> > > > > -	medfield_1,
> > > > > -	medfield_2,
> > > > > -	medfield_3,
> > > > > -	medfield_4,
> > > > > -	medfield_5,
> > > > > -
> > > > > +	medfield,
> > > > >  	baytrail,
> > > > >  	haswell,
> > > > >  };
> > > > > @@ -98,47 +92,12 @@ static struct dw_scl_sda_cfg hsw_config = {
> > > > >  };
> > > > >  
> > > > >  static struct  dw_pci_controller  dw_pci_controllers[] = {
> > > > > -	[medfield_0] = {
> > > > > -		.bus_num     = 0,
> > > > 
> > > > Wasn't that bus_num used to ensure stable bus numbers? Adding Mika.
> > > 
> > > That's right.
> > > 
> > > However, I don't think anybody really uses Medfield outside Intel so in
> > > that sense this patch should not break anything.
> > 
> > I think better to ask David who is closer to that Intel MID area.
> 
> OK, waiting for a reply from him here.

@David: ping


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Re: [PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[Wolfram Sang]

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On Mon, Jan 26, 2015 at 01:15:08PM +0100, Wolfram Sang wrote:
> On Sat, Jan 24, 2015 at 05:19:14AM +0100, Wolfram Sang wrote:
> > On Fri, Jan 23, 2015 at 03:04:06PM +0200, Andy Shevchenko wrote:
> > > On Fri, 2015-01-23 at 14:48 +0200, Mika Westerberg wrote:
> > > > On Fri, Jan 23, 2015 at 01:41:55PM +0100, Wolfram Sang wrote:
> > > > > On Fri, Jan 23, 2015 at 01:54:03PM +0200, Andy Shevchenko wrote:
> > > > > > There is no need to duplicate same data for each controller. If we need
> > > > > > specific stuff for a certain controller in the future we may add it later. The
> > > > > > patch leaves one controller per platform.
> > > > > > 
> > > > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563A2t4k+OOtxA@public.gmane.orgom>
> > > > > > ---
> > > > > >  drivers/i2c/busses/i2c-designware-pcidrv.c | 63 ++++++------------------------
> > > > > >  1 file changed, 11 insertions(+), 52 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > > index 5c6fca7..435a8ec 100644
> > > > > > --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > > +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > > @@ -40,13 +40,7 @@
> > > > > >  #define DRIVER_NAME "i2c-designware-pci"
> > > > > >  
> > > > > >  enum dw_pci_ctl_id_t {
> > > > > > -	medfield_0,
> > > > > > -	medfield_1,
> > > > > > -	medfield_2,
> > > > > > -	medfield_3,
> > > > > > -	medfield_4,
> > > > > > -	medfield_5,
> > > > > > -
> > > > > > +	medfield,
> > > > > >  	baytrail,
> > > > > >  	haswell,
> > > > > >  };
> > > > > > @@ -98,47 +92,12 @@ static struct dw_scl_sda_cfg hsw_config = {
> > > > > >  };
> > > > > >  
> > > > > >  static struct  dw_pci_controller  dw_pci_controllers[] = {
> > > > > > -	[medfield_0] = {
> > > > > > -		.bus_num     = 0,
> > > > > 
> > > > > Wasn't that bus_num used to ensure stable bus numbers? Adding Mika.
> > > > 
> > > > That's right.
> > > > 
> > > > However, I don't think anybody really uses Medfield outside Intel so in
> > > > that sense this patch should not break anything.
> > > 
> > > I think better to ask David who is closer to that Intel MID area.
> > 
> > OK, waiting for a reply from him here.
> 
> @David: ping

David: ping again


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Re: [PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[David Cohen]

On Thu, Feb 05, 2015 at 08:21:36PM +0100, Wolfram Sang wrote:
> On Mon, Jan 26, 2015 at 01:15:08PM +0100, Wolfram Sang wrote:
> > On Sat, Jan 24, 2015 at 05:19:14AM +0100, Wolfram Sang wrote:
> > > On Fri, Jan 23, 2015 at 03:04:06PM +0200, Andy Shevchenko wrote:
> > > > On Fri, 2015-01-23 at 14:48 +0200, Mika Westerberg wrote:
> > > > > On Fri, Jan 23, 2015 at 01:41:55PM +0100, Wolfram Sang wrote:
> > > > > > On Fri, Jan 23, 2015 at 01:54:03PM +0200, Andy Shevchenko wrote:
> > > > > > > There is no need to duplicate same data for each controller. If we need
> > > > > > > specific stuff for a certain controller in the future we may add it later. The
> > > > > > > patch leaves one controller per platform.
> > > > > > > 
> > > > > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> > > > > > > ---
> > > > > > >  drivers/i2c/busses/i2c-designware-pcidrv.c | 63 ++++++------------------------
> > > > > > >  1 file changed, 11 insertions(+), 52 deletions(-)
> > > > > > > 
> > > > > > > diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > > > index 5c6fca7..435a8ec 100644
> > > > > > > --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > > > +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > > > > > > @@ -40,13 +40,7 @@
> > > > > > >  #define DRIVER_NAME "i2c-designware-pci"
> > > > > > >  
> > > > > > >  enum dw_pci_ctl_id_t {
> > > > > > > -	medfield_0,
> > > > > > > -	medfield_1,
> > > > > > > -	medfield_2,
> > > > > > > -	medfield_3,
> > > > > > > -	medfield_4,
> > > > > > > -	medfield_5,
> > > > > > > -
> > > > > > > +	medfield,
> > > > > > >  	baytrail,
> > > > > > >  	haswell,
> > > > > > >  };
> > > > > > > @@ -98,47 +92,12 @@ static struct dw_scl_sda_cfg hsw_config = {
> > > > > > >  };
> > > > > > >  
> > > > > > >  static struct  dw_pci_controller  dw_pci_controllers[] = {
> > > > > > > -	[medfield_0] = {
> > > > > > > -		.bus_num     = 0,
> > > > > > 
> > > > > > Wasn't that bus_num used to ensure stable bus numbers? Adding Mika.
> > > > > 
> > > > > That's right.
> > > > > 
> > > > > However, I don't think anybody really uses Medfield outside Intel so in
> > > > > that sense this patch should not break anything.
> > > > 
> > > > I think better to ask David who is closer to that Intel MID area.
> > > 
> > > OK, waiting for a reply from him here.
> > 
> > @David: ping
> 
> David: ping again

Pong. Sorry for the delay.

There are actually few products based on Medfield reference board and
clovertrail+ as well uses medfield code. We need to keep the bus_num
there for these SFI platforms.

Br, David

Re: [PATCH v2 2/4] i2c: designware-pci: shrink dw_pci_controllers array

[Andy Shevchenko]

On Thu, 2015-02-05 at 14:56 -0800, David Cohen wrote:
> On Thu, Feb 05, 2015 at 08:21:36PM +0100, Wolfram Sang wrote:

> > > > > I think better to ask David who is closer to that Intel MID area.
> > > > 
> > > > OK, waiting for a reply from him here.
> > > 
> > > @David: ping
> > 
> > David: ping again
> 
> Pong. Sorry for the delay.
> 
> There are actually few products based on Medfield reference board and
> clovertrail+ as well uses medfield code. We need to keep the bus_num
> there for these SFI platforms.


Wolfram, I remove this patch and re-do and resend the former 4/4.


-- 
Andy Shevchenko <andriy.shevchenko-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Intel Finland Oy