From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Jarkko Nikula <jarkko.nikula@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-i2c@vger.kernel.org, Wolfram Sang <wsa@the-dreams.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Subject: [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support
Date: Wed, 15 Jun 2016 18:05:04 +0300 [thread overview]
Message-ID: <1466003107-19375-1-git-send-email-andriy.shevchenko@linux.intel.com> (raw)
Tested on bare metal (Intel Edison) by enumerating I2C GPIO expanders.
In v2:
- leave bus 3 at STD speed for Medfield
- be consistent with workflow, i.e. call ->setup, and _then_ assign to i2c
properties
- add a comment to explain magic numbers for Merrifield
- add an Ack for patch 3
Andy Shevchenko (3):
i2c: designware-pci: Make bus number allocation robust
i2c: designware-pci: Introduce Merrifield support
i2c: designware-pci: Sort header block alphabetically
drivers/i2c/busses/i2c-designware-core.h | 1 +
drivers/i2c/busses/i2c-designware-pcidrv.c | 143 +++++++++++++++++------------
2 files changed, 86 insertions(+), 58 deletions(-)
--
2.8.1
next reply other threads:[~2016-06-15 15:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-15 15:05 Andy Shevchenko [this message]
2016-06-15 15:05 ` [PATCH v2 1/3] i2c: designware-pci: Make bus number allocation robust Andy Shevchenko
2016-06-15 15:05 ` [PATCH v2 2/3] i2c: designware-pci: Introduce Merrifield support Andy Shevchenko
2016-06-15 15:05 ` [PATCH v2 3/3] i2c: designware-pci: Sort header block alphabetically Andy Shevchenko
2016-06-16 7:44 ` [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support Jarkko Nikula
2016-06-19 17:42 ` Wolfram Sang
2016-06-19 18:08 ` Andy Shevchenko
2016-06-19 18:17 ` Wolfram Sang
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