From mboxrd@z Thu Jan 1 00:00:00 1970 From: alanx.chiang@intel.com Subject: [PATCH v2 1/2] dt-bindings: at24: Add address-width property Date: Tue, 26 Jun 2018 14:22:07 +0800 Message-ID: <1529994128-26770-2-git-send-email-alanx.chiang@intel.com> References: <1529994128-26770-1-git-send-email-alanx.chiang@intel.com> Return-path: In-Reply-To: <1529994128-26770-1-git-send-email-alanx.chiang@intel.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-i2c@vger.kernel.org Cc: andy.yeh@intel.com, sakari.ailus@linux.intel.com, andriy.shevchenko@intel.com, rajmohan.mani@intel.com, andy.shevchenko@gmail.com, brgl@bgdev.pl, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, "alanx.chiang" List-Id: linux-i2c@vger.kernel.org From: "alanx.chiang" The AT24 series chips use 8-bit address by default. If some chips would like to support more than 8 bits, should add the compatible field for specfic chips in the driver. Provide a flexible way to determine the addressing bits through address-width in this patch. Signed-off-by: Alan Chiang Signed-off-by: Andy Yeh --- since v1: -- Remove the address-width field in the example. --- Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index 61d833a..9467482 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -72,6 +72,8 @@ Optional properties: - wp-gpios: GPIO to which the write-protect pin of the chip is connected. + - address-width : number of address bits (one of 8, 16). + Example: eeprom@52 { -- 2.7.4