From: Akash Asthana <akashast@codeaurora.org>
To: gregkh@linuxfoundation.org, agross@kernel.org,
bjorn.andersson@linaro.org, wsa@the-dreams.de,
broonie@kernel.org
Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, swboyd@chromium.org,
mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org,
linux-serial@vger.kernel.org, mka@chromium.org,
dianders@chromium.org, evgreen@codeaurora.org,
linux-kernel@vger.kernel.org,
Akash Asthana <akashast@codeaurora.org>
Subject: [PATCH V8 6/8] spi: spi-geni-qcom: Add interconnect support
Date: Tue, 23 Jun 2020 16:08:55 +0530 [thread overview]
Message-ID: <1592908737-7068-7-git-send-email-akashast@codeaurora.org> (raw)
In-Reply-To: <1592908737-7068-1-git-send-email-akashast@codeaurora.org>
Get the interconnect paths for SPI based Serial Engine device
and vote according to the current bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
Changes in V2:
- As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get
- As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- As per Matthias's comment, use helper ICC function from geni-se driver.
Changes in V4:
- Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly
to ICC core.
Changes in V5:
- Use icc_enable/disable in power on/off call.
- Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
from probe so that when resume/icc_enable is called NOC are running at
some non-zero value. No need to call icc_disable after BW vote because
device will resume and suspend before probe return and will leave ICC in
disabled state.
Changes in V6:
- No change
Changes in V7:
- As per Matthias's comment removed usage of peak_bw variable because we don't
have explicit peak requirement, we were voting peak = avg and this can be
tracked using single variable for avg bw.
Changes in V8:
- Adjust ICC vote per transfer, in multimessage transfer scenario.
- Move ICC voting to common API "geni_spi_set_clock_and_bw".
drivers/spi/spi-geni-qcom.c | 36 ++++++++++++++++++++++++++++++++----
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index f186906..7a2e579 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -192,7 +192,8 @@ static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
writel(word_len, se->base + SE_SPI_WORD_LEN);
}
-static int geni_spi_set_clock(struct spi_geni_master *mas, unsigned long clk_hz)
+static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
+ unsigned long clk_hz)
{
u32 clk_sel, m_clk_cfg, idx, div;
struct geni_se *se = &mas->se;
@@ -218,6 +219,12 @@ static int geni_spi_set_clock(struct spi_geni_master *mas, unsigned long clk_hz)
writel(clk_sel, se->base + SE_GENI_CLK_SEL);
writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
+ /* Set BW quota for CPU as driver supports FIFO mode only. */
+ se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
+ ret = geni_icc_set_bw(se);
+ if (ret)
+ return ret;
+
return 0;
}
@@ -259,7 +266,7 @@ static int setup_fifo_params(struct spi_device *spi_slv,
writel(cpol, se->base + SE_SPI_CPOL);
writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
- return geni_spi_set_clock(mas, spi_slv->max_speed_hz);
+ return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
}
static int spi_geni_prepare_message(struct spi_master *spi,
@@ -346,7 +353,7 @@ static void setup_fifo_xfer(struct spi_transfer *xfer,
/* Speed and bits per word can be overridden per transfer */
if (xfer->speed_hz != mas->cur_speed_hz) {
- ret = geni_spi_set_clock(mas, xfer->speed_hz);
+ ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
if (ret)
return;
}
@@ -620,6 +627,17 @@ static int spi_geni_probe(struct platform_device *pdev)
spin_lock_init(&mas->lock);
pm_runtime_enable(dev);
+ ret = geni_icc_get(&mas->se, NULL);
+ if (ret)
+ goto spi_geni_probe_runtime_disable;
+ /* Set the bus quota to a reasonable value for register access */
+ mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
+ mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
+
+ ret = geni_icc_set_bw(&mas->se);
+ if (ret)
+ goto spi_geni_probe_runtime_disable;
+
ret = spi_geni_init(mas);
if (ret)
goto spi_geni_probe_runtime_disable;
@@ -658,14 +676,24 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
+
+ ret = geni_se_resources_off(&mas->se);
+ if (ret)
+ return ret;
- return geni_se_resources_off(&mas->se);
+ return geni_icc_disable(&mas->se);
}
static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
+
+ ret = geni_icc_enable(&mas->se);
+ if (ret)
+ return ret;
return geni_se_resources_on(&mas->se);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-06-23 10:40 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
2020-06-23 10:38 ` [PATCH V8 1/8] soc: qcom: geni: Support for ICC voting Akash Asthana
2020-06-23 10:38 ` [PATCH V8 2/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana
2020-06-23 10:38 ` [PATCH V8 3/8] i2c: i2c-qcom-geni: Add interconnect support Akash Asthana
2020-06-23 10:38 ` [PATCH V8 4/8] tty: serial: qcom_geni_serial: " Akash Asthana
2020-06-23 10:38 ` [PATCH V8 5/8] spi: spi-geni-qcom: Combine the clock setting code Akash Asthana
2020-06-23 10:56 ` Mark Brown
2020-06-23 10:38 ` Akash Asthana [this message]
2020-06-23 10:57 ` [PATCH V8 6/8] spi: spi-geni-qcom: Add interconnect support Mark Brown
2020-06-23 10:38 ` [PATCH V8 7/8] spi: spi-qcom-qspi: " Akash Asthana
2020-06-23 10:57 ` Mark Brown
2020-06-23 10:38 ` [PATCH V8 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
2020-06-25 4:57 ` [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1592908737-7068-7-git-send-email-akashast@codeaurora.org \
--to=akashast@codeaurora.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dianders@chromium.org \
--cc=evgreen@codeaurora.org \
--cc=gregkh@linuxfoundation.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-i2c@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-serial@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=mgautam@codeaurora.org \
--cc=mka@chromium.org \
--cc=swboyd@chromium.org \
--cc=wsa@the-dreams.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).