Re: [PATCH 0/5] Qualcomm CCI I2C clock requirements enforcement

Mukesh Savaliya
2025-09-10T10:57:21Z

On 9/4/2025 8:01 PM, Konrad Dybcio wrote:
> The hardware requires the faster of the two (37.5 MHz as opposed to
> 19.2 MHz) clock rates to hit the required timings for I2C Fast+ Mode.
Should mention "source clock rates" to not confuse with derived
frequency/timings for Fast+ mode.>
> Additionally, the magic presets for electrical tuning registers on SoCs
> supporting that faster mode ("cci_v2" in the driver) are calculated
are/is calculated> based on that faster frequency.
>
> Moreover, while its unlikely that it would ever exhibit as an issue
> given CCI is a slow & tiny core, we do need to express a minimal voltage
> level for any given clock rate, which is where the (optional -
> backwards compat) OPP table addition comes in.
>
> This series helps ensure all these requirements are met.
>
> Patch 1 is a related but independent fix, can be picked right away
> Patch 5 can be functionally merged as-is, but depends on patch 2 for
> bindings
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> Konrad Dybcio (5):
> arm64: dts: qcom: sc8280xp: Fix CCI3 interrupt
> dt-bindings: i2c: qcom-cci: Allow operating-points-v2
> i2c: qcom-cci: Drop single-line wrappers
> i2c: qcom-cci: Add OPP table support and enforce FAST_PLUS requirements
> arm64: dts: qcom: sc8280xp: Add OPP table for CCI hosts
>
> .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 +
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 +++++++-
> drivers/i2c/busses/i2c-qcom-cci.c | 45 +++++++++++++++++-----
> 3 files changed, 52 insertions(+), 11 deletions(-)
> ---
> base-commit: 4ac65880ebca1b68495bd8704263b26c050ac010
> change-id: 20250904-topic-cci_updates-800fdc9bada4
>
> Best regards,