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charset="utf-8" Content-Transfer-Encoding: 7bit Subject: Re: [PATCH 5/8] arm64: dts: qcom: shikra: Add CCI definitions From: bod@kernel.org To: Nihal Kumar Gupta Cc: Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Andi Shyti , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Suresh Vankadara , Vikram Sharma In-Reply-To: <20260526-shikra-camss-review-v1-5-645d2c8c75a7@qti.qualcomm.com> References: <20260526-shikra-camss-review-v1-0-645d2c8c75a7@qti.qualcomm.com> <20260526-shikra-camss-review-v1-5-645d2c8c75a7@qti.qualcomm.com> Date: Thu, 28 May 2026 23:22:47 +0100 Message-Id: <178000696709.4557.9615154244947019683.b4-reply@b4> X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; 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a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A On 2026-05-26 22:42 +0530, Nihal Kumar Gupta wrote: > Qualcomm Shikra SoC has one Camera Control Interface (CCI) > containing two I2C hosts. > > Signed-off-by: Nihal Kumar Gupta > --- > arch/arm64/boot/dts/qcom/shikra.dtsi | 70 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi > index 6c47cf2a7ef26b4bb7d7f642a240b435cf5208d8..46de35971f629ded990827ebd76134e652758ce3 100644 > --- a/arch/arm64/boot/dts/qcom/shikra.dtsi > +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi > @@ -348,6 +348,38 @@ tlmm: pinctrl@500000 { > gpio-ranges = <&tlmm 0 0 165>; > wakeup-parent = <&mpm>; > > + cci_i2c0_default: cci-i2c0-default-state { > + /* SDA, SCL */ > + pins = "gpio36", "gpio37"; > + function = "cci_i2c0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci_i2c0_sleep: cci-i2c0-sleep-state { > + /* SDA, SCL */ > + pins = "gpio36", "gpio37"; > + function = "cci_i2c0"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + cci_i2c1_default: cci-i2c1-default-state { > + /* SDA, SCL */ > + pins = "gpio41", "gpio42"; > + function = "cci_i2c1"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci_i2c1_sleep: cci-i2c1-sleep-state { > + /* SDA, SCL */ > + pins = "gpio41", "gpio42"; > + function = "cci_i2c1"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > qup_uart0_default: qup-uart0-default-state { > pins = "gpio0", "gpio1"; > function = "qup0_se0"; > @@ -701,6 +733,44 @@ port@1 { > reg = <1>; > }; > }; > + > + }; > + > + cci: cci@5c1b000 { > + compatible = "qcom,shikra-cci", "qcom,msm8996-cci"; > + reg = <0x0 0x05c1b000 0x0 0x1000>; > + > + interrupts = ; > + > + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, > + <&gcc GCC_CAMSS_CCI_0_CLK>; > + clock-names = "ahb", > + "cci"; > + > + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; > + > + pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; > + pinctrl-1 = <&cci_i2c0_sleep &cci_i2c1_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > }; > > qupv3_0: geniqup@4ac0000 { > > -- > 2.34.1 > > Reviewed-by: Bryan O'Donoghue --- bod