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AJvYcCU6vSYn8VZhWXe2bhmBD3zHyYNyh7cLohZ1UxIaZ8eWrCEj26BIHfPqWRCI6BGgVGw8inihfwyqbt4=@vger.kernel.org X-Gm-Message-State: AOJu0YxiuczuGaWo1VoEXHz5Nj/pGgync7H+7EKsgm9QgZvLQPPJhh5r 07TBBdl6edZvKK+0quyeKv6fsDIpkES3kXUehVPuTMKSY+Kf9zpX+RqGqkkJnrk= X-Google-Smtp-Source: AGHT+IGKLIiZ8CzLoWVbsna5e8H1ecKT4pb77ee4/Gxsp14Hf8qUmzgZH4wljbjzNM628eXRI0oSuA== X-Received: by 2002:a17:907:3f1c:b0:a86:789c:2d07 with SMTP id a640c23a62f3a-a8a1d29bc25mr883588166b.4.1725552320548; Thu, 05 Sep 2024 09:05:20 -0700 (PDT) Received: from [192.168.0.25] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8a796a2bd6sm70318666b.189.2024.09.05.09.05.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Sep 2024 09:05:20 -0700 (PDT) Message-ID: <1914fc07-d7be-4747-971b-40ef360d050a@linaro.org> Date: Thu, 5 Sep 2024 17:05:19 +0100 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/7] i2c: qcom-cci: Stop complaining about DT set clock rate To: Konrad Dybcio , Richard Acayan , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti , Todor Tomov , Mauro Carvalho Chehab , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, linux-media@vger.kernel.org Cc: Vladimir Zapolskiy References: <20240904020448.52035-9-mailingradian@gmail.com> <20240904020448.52035-12-mailingradian@gmail.com> <917917cc-3e78-4ab6-8fa4-82d9a6fe3fdd@kernel.org> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <917917cc-3e78-4ab6-8fa4-82d9a6fe3fdd@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 05/09/2024 14:57, Konrad Dybcio wrote: > On 4.09.2024 4:04 AM, Richard Acayan wrote: >> From: Bryan O'Donoghue >> >> It is common practice in the downstream and upstream CCI dt to set CCI >> clock rates to 19.2 MHz. It appears to be fairly common for initial code to >> set the CCI clock rate to 37.5 MHz. >> >> Applying the widely used CCI clock rates from downstream ought not to cause >> warning messages in the upstream kernel where our general policy is to >> usually copy downstream hardware clock rates across the range of Qualcomm >> drivers. >> >> Drop the warning it is pervasive across CAMSS users but doesn't add any >> information or warrant any changes to the DT to align the DT clock rate to >> the bootloader clock rate. >> >> Signed-off-by: Bryan O'Donoghue >> Reviewed-by: Vladimir Zapolskiy >> Link: https://lore.kernel.org/linux-arm-msm/20240824115900.40702-1-bryan.odonoghue@linaro.org >> Signed-off-by: Richard Acayan >> --- > > I.. am not sure this is really a problem? On some platforms the core > clock is only 19.2 Mhz, but e.g. on sdm845 we have: > > static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = { > F(19200000, P_BI_TCXO, 1, 0, 0), > F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), > F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), > F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), > { } > }; CCI latches the code from DT and I assume that people submitting dts have actually tested their sensors when they do so. The complaint about not being 19.2 MHz is surely not valid since, it can be any number of frequencies. Its a redundant and useless warning. We can do extra work to align to a set of frequencies sure but, the warning is not a warning about a real thing. --- bod