Re: [PATCH 2/2] dt-bindings: i2c: snps,designware-i2c: add bus-loading and clk-freq-optimized

[Krzysztof Kozlowski <krzk@kernel.org>]

On 25/09/2024 10:04, Michael Wu wrote:
> Since there are no registers controlling the hardware parameters
> IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION, their values can only be
> noted in the device tree.
> 
> "bus-loading" is used to declare the value of IC_CAP_LOADING, and
> "clk-freq-optimized" is used to declare IC_CLK_FREQ_OPTIMIZATION = 1.
> 
> Signed-off-by: Michael Wu <michael.wu@kneron.us>

<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.

You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time.

Please kindly resend and include all necessary To/Cc entries.
</form letter>

> ---
>  .../bindings/i2c/snps,designware-i2c.yaml     | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
> index 60035a787e5c..f954f5014a00 100644
> --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
> @@ -87,6 +87,16 @@ properties:
>        This value is used to compute the tHIGH period.
>      default: 300
>  
> +  bus-loading:
> +    description: |
> +      This property should be 100 or 400 for high speed mode.
> +      This value is used to compute the tHIGH period and the tLOW period.

How? This wasn't ever tested obviously... Missing units in property name
(or ref but units are preferred).

> +    default: 100
> +
> +  clk_freq_optimized:

No underscores.

> +    description: |
> +      Thie property is used to declare whether the internal latency is reduced.

Your descriptions don't tell me much. Drop redundant parts "This
property" and instead describe the hardware aspect of this property.


> +
>    dmas:
>      items:
>        - description: TX DMA Channel
> @@ -146,4 +156,13 @@ examples:
>        interrupts = <8>;
>        clocks = <&ahb_clk>;
>      };
> +  - |
> +    i2c@ce500000 {

No, no need.



Best regards,
Krzysztof