Re: parport (i2c bus) maximum speed

[Jean Delvare <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>]

Hi Petr,

On Fri, 13 Jun 2008 15:44:12 +0200, Petr Jakeš wrote:
> I am thinking about to build an I2C-parport HW adapter. I would like to
> know, what is the maximum speed one can get on the I2C bus using parport HW
> adapter. I expect 100kbps is a standard speed but if it possible to go to
> 400k it will be great.
> If it is not possible to get 400kbps speed using the parport, other hints
> are appreciated of course :-)

Our current i2c-algo-bit implementation can't go faster than 250 kbps
by design. I think I remember trying it and it was working fine. But if
memory serves the actual speed ended up being significantly less than
250 kpbs, maybe 160 kbps. Just like you don't actually get 100 kbps
when you ask for 100 kbps. I guess that there's latency in switching
the parport pins, which becomes visible as the speed increases.

If you plan on doing fast I2C over parport, then I think you want to
give up on bit-banging and instead control an I2C master beyond the
parallel port. That way you take benefit of the parallel aspect of
parport and you should be able to reach 400 kbps. Using a chip we
already have abstracted support for (PCF8584 or PCA9564) this shouldn't
be too difficult.

-- 
Jean Delvare

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