[PATCH 00/03] i2c: i2c-sh_mobile update for SH-Mobile ARM

[PATCH 00/03] i2c: i2c-sh_mobile update for SH-Mobile ARM

[Magnus Damm]

i2c: i2c-sh_mobile update for SH-Mobile ARM

[PATCH 01/03] i2c: i2c-sh_mobile register access code break out
[PATCH 02/03] i2c: i2c-sh_mobile support for new ICIC bits
[PATCH 03/03] i2c: i2c-sh_mobile kconfig update for SH-Mobile ARM

These patches add support for a newer version of the IIC block
to the i2c-sh_mobile and enables the driver on SH-Mobile ARM.

Perhaps suitable for the SH tree?

---

 drivers/i2c/busses/Kconfig         |    2 
 drivers/i2c/busses/i2c-sh_mobile.c |  121 ++++++++++++++++++++++++------------
 2 files changed, 85 insertions(+), 38 deletions(-)

[PATCH 01/03] i2c: i2c-sh_mobile register access code break out

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Break out register access functions in the
i2c-sh_mobile driver. This update should not
change any driver logic.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 drivers/i2c/busses/i2c-sh_mobile.c |   90 +++++++++++++++++++++---------------
 1 file changed, 53 insertions(+), 37 deletions(-)

--- 0001/drivers/i2c/busses/i2c-sh_mobile.c
+++ work/drivers/i2c/busses/i2c-sh_mobile.c	2010-03-11 15:16:09.000000000 +0900
@@ -131,12 +131,12 @@ struct sh_mobile_i2c_data {
 #define NORMAL_SPEED		100000 /* FAST_SPEED 400000 */
 
 /* Register offsets */
-#define ICDR(pd)		(pd->reg + 0x00)
-#define ICCR(pd)		(pd->reg + 0x04)
-#define ICSR(pd)		(pd->reg + 0x08)
-#define ICIC(pd)		(pd->reg + 0x0c)
-#define ICCL(pd)		(pd->reg + 0x10)
-#define ICCH(pd)		(pd->reg + 0x14)
+#define ICDR			0x00
+#define ICCR			0x04
+#define ICSR			0x08
+#define ICIC			0x0c
+#define ICCL			0x10
+#define ICCH			0x14
 
 /* Register bits */
 #define ICCR_ICE		0x80
@@ -159,6 +159,22 @@ struct sh_mobile_i2c_data {
 #define ICIC_WAITE		0x02
 #define ICIC_DTEE		0x01
 
+static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
+{
+	iowrite8(data, pd->reg + offs);
+}
+
+static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
+{
+	return ioread8(pd->reg + offs);
+}
+
+static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
+			unsigned char set, unsigned char clr)
+{
+	iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
+}
+
 static void activate_ch(struct sh_mobile_i2c_data *pd)
 {
 	unsigned long i2c_clk;
@@ -196,24 +212,24 @@ static void activate_ch(struct sh_mobile
 		pd->icch = (u_int8_t)(num/denom);
 
 	/* Enable channel and configure rx ack */
-	iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
+	iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 
 	/* Mask all interrupts */
-	iowrite8(0, ICIC(pd));
+	iic_wr(pd, ICIC, 0);
 
 	/* Set the clock */
-	iowrite8(pd->iccl, ICCL(pd));
-	iowrite8(pd->icch, ICCH(pd));
+	iic_wr(pd, ICCL, pd->iccl);
+	iic_wr(pd, ICCH, pd->icch);
 }
 
 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
 {
 	/* Clear/disable interrupts */
-	iowrite8(0, ICSR(pd));
-	iowrite8(0, ICIC(pd));
+	iic_wr(pd, ICSR, 0);
+	iic_wr(pd, ICIC, 0);
 
 	/* Disable channel */
-	iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
+	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 
 	/* Disable clock and mark device as idle */
 	clk_disable(pd->clk);
@@ -232,35 +248,35 @@ static unsigned char i2c_op(struct sh_mo
 
 	switch (op) {
 	case OP_START: /* issue start and trigger DTE interrupt */
-		iowrite8(0x94, ICCR(pd));
+		iic_wr(pd, ICCR, 0x94);
 		break;
 	case OP_TX_FIRST: /* disable DTE interrupt and write data */
-		iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
-		iowrite8(data, ICDR(pd));
+		iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+		iic_wr(pd, ICDR, data);
 		break;
 	case OP_TX: /* write data */
-		iowrite8(data, ICDR(pd));
+		iic_wr(pd, ICDR, data);
 		break;
 	case OP_TX_STOP: /* write data and issue a stop afterwards */
-		iowrite8(data, ICDR(pd));
-		iowrite8(0x90, ICCR(pd));
+		iic_wr(pd, ICDR, data);
+		iic_wr(pd, ICCR, 0x90);
 		break;
 	case OP_TX_TO_RX: /* select read mode */
-		iowrite8(0x81, ICCR(pd));
+		iic_wr(pd, ICCR, 0x81);
 		break;
 	case OP_RX: /* just read data */
-		ret = ioread8(ICDR(pd));
+		ret = iic_rd(pd, ICDR);
 		break;
 	case OP_RX_STOP: /* enable DTE interrupt, issue stop */
-		iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
-			 ICIC(pd));
-		iowrite8(0xc0, ICCR(pd));
+		iic_wr(pd, ICIC,
+		       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+		iic_wr(pd, ICCR, 0xc0);
 		break;
 	case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
-		iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
-			 ICIC(pd));
-		ret = ioread8(ICDR(pd));
-		iowrite8(0xc0, ICCR(pd));
+		iic_wr(pd, ICIC,
+		       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+		ret = iic_rd(pd, ICDR);
+		iic_wr(pd, ICCR, 0xc0);
 		break;
 	}
 
@@ -366,7 +382,7 @@ static irqreturn_t sh_mobile_i2c_isr(int
 	unsigned char sr;
 	int wakeup;
 
-	sr = ioread8(ICSR(pd));
+	sr = iic_rd(pd, ICSR);
 	pd->sr |= sr; /* remember state */
 
 	dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
@@ -375,7 +391,7 @@ static irqreturn_t sh_mobile_i2c_isr(int
 
 	if (sr & (ICSR_AL | ICSR_TACK)) {
 		/* don't interrupt transaction - continue to issue stop */
-		iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
+		iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
 		wakeup = 0;
 	} else if (pd->msg->flags & I2C_M_RD)
 		wakeup = sh_mobile_i2c_isr_rx(pd);
@@ -383,7 +399,7 @@ static irqreturn_t sh_mobile_i2c_isr(int
 		wakeup = sh_mobile_i2c_isr_tx(pd);
 
 	if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
-		iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
+		iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 
 	if (wakeup) {
 		pd->sr |= SW_DONE;
@@ -401,21 +417,21 @@ static int start_ch(struct sh_mobile_i2c
 	}
 
 	/* Initialize channel registers */
-	iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
+	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 
 	/* Enable channel and configure rx ack */
-	iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
+	iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 
 	/* Set the clock */
-	iowrite8(pd->iccl, ICCL(pd));
-	iowrite8(pd->icch, ICCH(pd));
+	iic_wr(pd, ICCL, pd->iccl);
+	iic_wr(pd, ICCH, pd->icch);
 
 	pd->msg = usr_msg;
 	pd->pos = -1;
 	pd->sr = 0;
 
 	/* Enable all interrupts to begin with */
-	iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
+	iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 	return 0;
 }
 
@@ -450,7 +466,7 @@ static int sh_mobile_i2c_xfer(struct i2c
 
 		retry_count = 1000;
 again:
-		val = ioread8(ICSR(pd));
+		val = iic_rd(pd, ICSR);
 
 		dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 

[PATCH 02/03] i2c: i2c-sh_mobile support for new ICIC bits

[Magnus Damm]

From: Magnus Damm <damm-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>

Add support for a new version of the IIC block
found in the SH-Mobile ARM line of processors.

Prototype patch written by Nishimoto-san.
Tested on sh7377 and sh7372.

Signed-off-by: NISHIMOTO Hiroki <nishimoto.hiroki-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Magnus Damm <damm-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>
---

 drivers/i2c/busses/i2c-sh_mobile.c |   31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

--- 0026/drivers/i2c/busses/i2c-sh_mobile.c
+++ work/drivers/i2c/busses/i2c-sh_mobile.c	2010-03-11 15:33:09.000000000 +0900
@@ -118,8 +118,10 @@ struct sh_mobile_i2c_data {
 	struct i2c_adapter adap;
 
 	struct clk *clk;
+	u_int8_t icic;
 	u_int8_t iccl;
 	u_int8_t icch;
+	u_int8_t flags;
 
 	spinlock_t lock;
 	wait_queue_head_t wait;
@@ -128,6 +130,8 @@ struct sh_mobile_i2c_data {
 	int sr;
 };
 
+#define IIC_FLAG_HAS_ICIC67	(1 << 0)
+
 #define NORMAL_SPEED		100000 /* FAST_SPEED 400000 */
 
 /* Register offsets */
@@ -154,6 +158,8 @@ struct sh_mobile_i2c_data {
 #define ICSR_WAIT		0x02
 #define ICSR_DTE		0x01
 
+#define ICIC_ICCLB8		0x80
+#define ICIC_ICCHB8		0x40
 #define ICIC_ALE		0x08
 #define ICIC_TACKE		0x04
 #define ICIC_WAITE		0x02
@@ -161,6 +167,9 @@ struct sh_mobile_i2c_data {
 
 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
 {
+	if (offs == ICIC)
+		data |= pd->icic;
+
 	iowrite8(data, pd->reg + offs);
 }
 
@@ -202,6 +211,14 @@ static void activate_ch(struct sh_mobile
 	else
 		pd->iccl = (u_int8_t)(num/denom);
 
+	/* one more bit of ICCL in ICIC */
+	if (pd->flags & IIC_FLAG_HAS_ICIC67) {
+		if ((num/denom) > 0xff)
+			pd->icic |= ICIC_ICCLB8;
+		else
+			pd->icic &= ~ICIC_ICCLB8;
+	}
+
 	/* Calculate the value for icch. From the data sheet:
 	   icch = (p clock / transfer rate) * (H / (L + H)) */
 	num = i2c_clk * 4;
@@ -211,6 +228,14 @@ static void activate_ch(struct sh_mobile
 	else
 		pd->icch = (u_int8_t)(num/denom);
 
+	/* one more bit of ICCH in ICIC */
+	if (pd->flags & IIC_FLAG_HAS_ICIC67) {
+		if ((num/denom) > 0xff)
+			pd->icic |= ICIC_ICCHB8;
+		else
+			pd->icic &= ~ICIC_ICCHB8;
+	}
+
 	/* Enable channel and configure rx ack */
 	iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 
@@ -591,6 +616,12 @@ static int sh_mobile_i2c_probe(struct pl
 		goto err_irq;
 	}
 
+	/* The IIC blocks on SH-Mobile ARM processors
+	 * come with two new bits in ICIC.
+	 */
+	if (size > 0x17)
+		pd->flags |= IIC_FLAG_HAS_ICIC67;
+
 	/* Enable Runtime PM for this device.
 	 *
 	 * Also tell the Runtime PM core to ignore children

[PATCH 03/03] i2c: i2c-sh_mobile kconfig update for SH-Mobile ARM

[Magnus Damm]

From: Magnus Damm <damm-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>

Update the Kconfig entry for the i2c-sh_mobile driver to
enable build on SH-Mobile ARM platforms

Signed-off-by: Kuninori Morimoto <morimoto.kuninori-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Magnus Damm <damm-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>
---

 drivers/i2c/busses/Kconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- 0001/drivers/i2c/busses/Kconfig
+++ work/drivers/i2c/busses/Kconfig	2010-03-11 18:41:50.000000000 +0900
@@ -520,7 +520,7 @@ config I2C_SH7760
 
 config I2C_SH_MOBILE
 	tristate "SuperH Mobile I2C Controller"
-	depends on SUPERH
+	depends on SUPERH || ARCH_SHMOBILE
 	help
 	  If you say yes to this option, support will be included for the
 	  built-in I2C interface on the Renesas SH-Mobile processor.

Re: [PATCH 00/03] i2c: i2c-sh_mobile update for SH-Mobile ARM

[Ben Dooks]

On Thu, Mar 11, 2010 at 07:05:26PM +0900, Magnus Damm wrote:
> i2c: i2c-sh_mobile update for SH-Mobile ARM
> 
> [PATCH 01/03] i2c: i2c-sh_mobile register access code break out
> [PATCH 02/03] i2c: i2c-sh_mobile support for new ICIC bits
> [PATCH 03/03] i2c: i2c-sh_mobile kconfig update for SH-Mobile ARM
> 
> These patches add support for a newer version of the IIC block
> to the i2c-sh_mobile and enables the driver on SH-Mobile ARM.
> 
> Perhaps suitable for the SH tree?

I'll add these to i2c-next once I restart it in a few days
time.

-- 
Ben (ben-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'

Re: [PATCH 00/03] i2c: i2c-sh_mobile update for SH-Mobile ARM

[Paul Mundt]

On Mon, Mar 15, 2010 at 06:30:05AM +0000, Ben Dooks wrote:
> On Thu, Mar 11, 2010 at 07:05:26PM +0900, Magnus Damm wrote:
> > i2c: i2c-sh_mobile update for SH-Mobile ARM
> > 
> > [PATCH 01/03] i2c: i2c-sh_mobile register access code break out
> > [PATCH 02/03] i2c: i2c-sh_mobile support for new ICIC bits
> > [PATCH 03/03] i2c: i2c-sh_mobile kconfig update for SH-Mobile ARM
> > 
> > These patches add support for a newer version of the IIC block
> > to the i2c-sh_mobile and enables the driver on SH-Mobile ARM.
> > 
> > Perhaps suitable for the SH tree?
> 
> I'll add these to i2c-next once I restart it in a few days
> time.
> 
I still don't see these in -next, so I suppose I'll just roll these in to
the genesis tree, especially since we have outstanding patches that
depend on these.

Re: [PATCH] ARM: mach-shmobile: add INTCS macros

[Paul Mundt]

On Thu, Mar 11, 2010 at 02:30:30PM +0900, Magnus Damm wrote:
> Add SH-Mobile ARM INTCS macros for the INTCS controller.

On Thu, Mar 11, 2010 at 03:52:33PM +0900, Magnus Damm wrote:
> Add support for the sh7367 INTCS interrupt controller.
> 
> INTCS is the interrupt controller for the sh7367 SuperH
> processor core. It is tied into the INTCA interrupt
> controller which interfaces to the ARM processor.
> 
> INTCS support is implemented using a new INTC table
> together with a chained interrupt handler that ties
> into the already supported INTCA controller.

On Thu, Mar 11, 2010 at 07:05:26PM +0900, Magnus Damm wrote:
> i2c: i2c-sh_mobile update for SH-Mobile ARM
> 
> [PATCH 01/03] i2c: i2c-sh_mobile register access code break out
> [PATCH 02/03] i2c: i2c-sh_mobile support for new ICIC bits
> [PATCH 03/03] i2c: i2c-sh_mobile kconfig update for SH-Mobile ARM
> 
> These patches add support for a newer version of the IIC block
> to the i2c-sh_mobile and enables the driver on SH-Mobile ARM.
> 
Applied, thanks.