[PATCH 0/6] decode-dimms: Fix and improve DDR3 support

[PATCH 0/6] decode-dimms: Fix and improve DDR3 support

[Jean Delvare]

Today I have been working on decode-dimms' DDR3 support and came up
with 2 fixes and 4 improvements:

[1/6] Fix tRAS value
[2/6] Fix core timings rounding
[3/6] Store time bases, don't print them
[4/6] Use fine time base
[5/6] Repeat core timings as time values
[6/6] Print core timings at all supported standard speeds

Note : if anyone has SPD data for DDR3-1866 or DDR3-2133, please send
them to me so that I can test my code better.

-- 
Jean Delvare

[PATCH 1/6] DDR3: Fix tRAS value

[Jean Delvare]

DDR3: Use the right nibble from byte 21 as the MSB of tRAS.
---
 eeprom/decode-dimms |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- i2c-tools.orig/eeprom/decode-dimms	2013-04-10 14:09:02.415218409 +0200
+++ i2c-tools/eeprom/decode-dimms	2013-04-10 14:11:18.839376112 +0200
@@ -1393,7 +1393,7 @@ sub decode_ddr3_sdram($)
 	$taa  = int($bytes->[16] / $bytes->[12]);
 	$trcd = int($bytes->[18] / $bytes->[12]);
 	$trp  = int($bytes->[20] / $bytes->[12]);
-	$tras = int((($bytes->[21] >> 4) * 256 + $bytes->[22]) / $bytes->[12]);
+	$tras = int(((($bytes->[21] & 0x0f) << 8) + $bytes->[22]) / $bytes->[12]);
 
 	printl("tCL-tRCD-tRP-tRAS", join("-", $taa, $trcd, $trp, $tras));
 

-- 
Jean Delvare

[PATCH 2/6] DDR3: Fix core timings rounding

[Jean Delvare]

DDR3: Round core timings up, not down.
---
 eeprom/decode-dimms |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

--- i2c-tools.orig/eeprom/decode-dimms	2013-04-10 14:29:35.349802212 +0200
+++ i2c-tools/eeprom/decode-dimms	2013-04-10 14:30:19.753833437 +0200
@@ -1390,10 +1390,10 @@ sub decode_ddr3_sdram($)
 	my $trp;
 	my $tras;
 
-	$taa  = int($bytes->[16] / $bytes->[12]);
-	$trcd = int($bytes->[18] / $bytes->[12]);
-	$trp  = int($bytes->[20] / $bytes->[12]);
-	$tras = int(((($bytes->[21] & 0x0f) << 8) + $bytes->[22]) / $bytes->[12]);
+	$taa  = ceil($bytes->[16] / $bytes->[12]);
+	$trcd = ceil($bytes->[18] / $bytes->[12]);
+	$trp  = ceil($bytes->[20] / $bytes->[12]);
+	$tras = ceil(((($bytes->[21] & 0x0f) << 8) + $bytes->[22]) / $bytes->[12]);
 
 	printl("tCL-tRCD-tRP-tRAS", join("-", $taa, $trcd, $trp, $tras));
 

-- 
Jean Delvare

[PATCH 3/6] DDR3: Store time bases, don't print them

[Jean Delvare]

DDR3: Don't print the medium and fine time bases, they aren't directly
useful to the user. Simply store them for later use.
---
 eeprom/decode-dimms |   18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

--- i2c-tools.orig/eeprom/decode-dimms	2013-04-10 14:30:19.753833437 +0200
+++ i2c-tools/eeprom/decode-dimms	2013-04-10 15:37:24.481817216 +0200
@@ -1335,6 +1335,7 @@ sub decode_ddr3_sdram($)
 	my $bytes = shift;
 	my $temp;
 	my $ctime;
+	my ($ftb, $mtb);
 
 	my @module_types = ("Undefined", "RDIMM", "UDIMM", "SO-DIMM",
 			    "Micro-DIMM", "Mini-RDIMM", "Mini-UDIMM",
@@ -1346,18 +1347,17 @@ sub decode_ddr3_sdram($)
 					$module_types[$bytes->[3]] :
 					sprintf("Reserved (0x%.2X)", $bytes->[3]));
 
+# time bases
+	if (($bytes->[9] & 0x0f) == 0 || $bytes->[11] == 0) {
+		print STDERR "Invalid time base divisor, can't decode\n";
+		return;
+	}
+	$ftb = ($bytes->[9] >> 4) / ($bytes->[9] & 0x0f);
+	$mtb = $bytes->[10] / $bytes->[11];
+
 # speed
 	prints("Memory Characteristics");
 
-	my $dividend = ($bytes->[9] >> 4) & 15;
-	my $divisor  = $bytes->[9] & 15;
-	printl("Fine time base", sprintf("%.3f", $dividend / $divisor) . " ps");
-
-	$dividend = $bytes->[10];
-	$divisor  = $bytes->[11];
-	my $mtb = $dividend / $divisor;
-	printl("Medium time base", tns3($mtb));
-
 	$ctime = $bytes->[12] * $mtb;
 	my $ddrclk = 2 * (1000 / $ctime);
 	my $tbits = 1 << (($bytes->[8] & 7) + 3);

-- 
Jean Delvare

[PATCH 4/6] DDR3: Use fine time base

[Jean Delvare]

DDR3: Decode the FTB fields of tCk, tAA, tRCD, tRP and tRC.
---
 eeprom/decode-dimms |   25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

--- i2c-tools.orig/eeprom/decode-dimms	2013-04-10 14:12:37.739202969 +0200
+++ i2c-tools/eeprom/decode-dimms	2013-04-10 14:17:03.383357005 +0200
@@ -1329,6 +1329,17 @@ sub decode_ddr2_sdram($)
 	printl_cond($bytes->[46], "PLL Relock Time", $bytes->[46] . " us");
 }
 
+# Return combined time in ns
+sub ddr3_mtb_ftb($$$$)
+{
+	my ($byte1, $byte2, $mtb, $ftb) = @_;
+
+	# byte1 is unsigned in ns, but byte2 is signed in ps
+	$byte2 -= 0x100 if $byte2 & 0x80;
+
+	return $byte1 * $mtb + $byte2 * $ftb / 1000;
+}
+
 # Parameter: EEPROM bytes 0-127 (using 3-76)
 sub decode_ddr3_sdram($)
 {
@@ -1358,7 +1369,7 @@ sub decode_ddr3_sdram($)
 # speed
 	prints("Memory Characteristics");
 
-	$ctime = $bytes->[12] * $mtb;
+	$ctime = ddr3_mtb_ftb($bytes->[12], $bytes->[34], $mtb, $ftb);
 	my $ddrclk = 2 * (1000 / $ctime);
 	my $tbits = 1 << (($bytes->[8] & 7) + 3);
 	my $pcclk = int ($ddrclk * $tbits / 8);
@@ -1390,12 +1401,12 @@ sub decode_ddr3_sdram($)
 	my $trp;
 	my $tras;
 
-	$taa  = ceil($bytes->[16] / $bytes->[12]);
-	$trcd = ceil($bytes->[18] / $bytes->[12]);
-	$trp  = ceil($bytes->[20] / $bytes->[12]);
-	$tras = ceil(((($bytes->[21] & 0x0f) << 8) + $bytes->[22]) / $bytes->[12]);
+	$taa  = ddr3_mtb_ftb($bytes->[16], $bytes->[35], $mtb, $ftb);
+	$trcd = ddr3_mtb_ftb($bytes->[18], $bytes->[36], $mtb, $ftb);
+	$trp  = ddr3_mtb_ftb($bytes->[20], $bytes->[37], $mtb, $ftb);
+	$tras = ((($bytes->[21] & 0x0f) << 8) + $bytes->[22]) * $mtb;
 
-	printl("tCL-tRCD-tRP-tRAS", join("-", $taa, $trcd, $trp, $tras));
+	printl("tCL-tRCD-tRP-tRAS", ddr_core_timings(ceil($taa / $ctime), $ctime, $trcd, $trp, $tras));
 
 # latencies
 	my $highestCAS = 0;
@@ -1417,7 +1428,7 @@ sub decode_ddr3_sdram($)
 	printl("Minimum Row Active to Row Active Delay (tRRD)",
 		tns3($bytes->[19] * $mtb));
 	printl("Minimum Active to Auto-Refresh Delay (tRC)",
-		tns3((((($bytes->[21] >> 4) & 15) << 8) + $bytes->[23]) * $mtb));
+		tns3(ddr3_mtb_ftb((($bytes->[21] & 0xf0) << 4) + $bytes->[23], $bytes->[38], $mtb, $ftb)));
 	printl("Minimum Recovery Delay (tRFC)",
 		tns3((($bytes->[25] << 8) + $bytes->[24]) * $mtb));
 	printl("Minimum Write to Read CMD Delay (tWTR)",

-- 
Jean Delvare

[PATCH 5/6] DDR3: Repeat core timings as time values

[Jean Delvare]

DDR3: Repeat tCK, tAA, tRCD, tRP and tRAS values, so that they show up
no only as cycle counts but also absolute time values.
---
 eeprom/decode-dimms |    5 +++++
 1 file changed, 5 insertions(+)

--- i2c-tools.orig/eeprom/decode-dimms	2013-04-10 15:42:32.755478921 +0200
+++ i2c-tools/eeprom/decode-dimms	2013-04-10 15:52:46.527793347 +0200
@@ -1424,9 +1424,14 @@ sub decode_ddr3_sdram($)
 # more timing information
 	prints("Timing Parameters");
 
+	printl("Minimum Cycle Time (tCK)", tns3($ctime));
+	printl("Minimum CAS Latency Time (tAA)", tns3($taa));
 	printl("Minimum Write Recovery time (tWR)", tns3($bytes->[17] * $mtb));
+	printl("Minimum RAS# to CAS# Delay (tRCD)", tns3($trcd));
 	printl("Minimum Row Active to Row Active Delay (tRRD)",
 		tns3($bytes->[19] * $mtb));
+	printl("Minimum Row Precharge Delay (tRP)", tns3($trp));
+	printl("Minimum Active to Precharge Delay (tRAS)", tns3($tras));
 	printl("Minimum Active to Auto-Refresh Delay (tRC)",
 		tns3(ddr3_mtb_ftb((($bytes->[21] & 0xf0) << 4) + $bytes->[23], $bytes->[38], $mtb, $ftb)));
 	printl("Minimum Recovery Delay (tRFC)",

-- 
Jean Delvare

[PATCH 6/6] DDR3: Print core timings at all supported standard speeds

[Jean Delvare]

Print timings at standard DDR3 speeds. This makes it easier to figure
out which memory modules will work well together.
---
 eeprom/decode-dimms |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Note : if anyone has SPD data for DDR3-1866 or DDR3-2133, please send
them to me so that I can test my code better.

--- i2c-tools.orig/eeprom/decode-dimms	2013-04-10 17:33:33.755706113 +0200
+++ i2c-tools/eeprom/decode-dimms	2013-04-10 21:53:08.674615604 +0200
@@ -1421,6 +1421,25 @@ sub decode_ddr3_sdram($)
 	}
 	printl("Supported CAS Latencies (tCL)", cas_latencies(keys %cas));
 
+# standard DDR3 speeds
+	prints("Timings at Standard Speeds");
+	foreach my $ctime_at_speed (7.5/8, 7.5/7, 1.25, 1.5, 1.875, 2.5) {
+		my $best_cas = $highestCAS;
+
+		# Find min CAS latency at this speed
+		for ($ii = 14; $ii >= 0; $ii--) {
+			next unless ($cas_sup & (1 << $ii));
+			if (ceil($taa / $ctime_at_speed) <= $ii + 4) {
+				$best_cas = $ii + 4;
+			}
+		}
+
+		printl_cond($ctime_at_speed >= $ctime,
+			    "tCL-tRCD-tRP-tRAS" . as_ddr(3, $ctime_at_speed),
+			    ddr_core_timings($best_cas, $ctime_at_speed,
+					     $trcd, $trp, $tras));
+	}
+
 # more timing information
 	prints("Timing Parameters");
 


-- 
Jean Delvare