From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Emilio Lopez <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>,
kevin-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org,
sunny-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org,
shuge-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCHv3 1/6] i2c: sunxi: Add Allwinner A1X i2c driver
Date: Wed, 5 Jun 2013 15:39:47 +0200 [thread overview]
Message-ID: <20130605133945.GA2934@katana> (raw)
In-Reply-To: <1369648843-1640-2-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
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> +#define SUNXI_I2C_ADDR_REG (0x00)
> +#define SUNXI_I2C_ADDR_ADDR(v) ((v & 0x7f) << 1)
> +#define SUNXI_I2C_XADDR_REG (0x04)
> +#define SUNXI_I2C_DATA_REG (0x08)
> +#define SUNXI_I2C_CNTR_REG (0x0c)
> +#define SUNXI_I2C_CNTR_ASSERT_ACK BIT(2)
> +#define SUNXI_I2C_CNTR_INT_FLAG BIT(3)
> +#define SUNXI_I2C_CNTR_MASTER_STOP BIT(4)
> +#define SUNXI_I2C_CNTR_MASTER_START BIT(5)
> +#define SUNXI_I2C_CNTR_BUS_ENABLE BIT(6)
> +#define SUNXI_I2C_CNTR_INT_ENABLE BIT(7)
> +#define SUNXI_I2C_STA_REG (0x10)
> +#define SUNXI_I2C_STA_BUS_ERROR (0x00)
> +#define SUNXI_I2C_STA_START (0x08)
> +#define SUNXI_I2C_STA_START_REPEAT (0x10)
> +#define SUNXI_I2C_STA_MASTER_WADDR_ACK (0x18)
> +#define SUNXI_I2C_STA_MASTER_WADDR_NAK (0x20)
> +#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK (0x28)
> +#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK (0x30)
> +#define SUNXI_I2C_STA_MASTER_RADDR_ACK (0x40)
> +#define SUNXI_I2C_STA_MASTER_RADDR_NAK (0x48)
> +#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK (0x50)
> +#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK (0x58)
> +#define SUNXI_I2C_CCR_REG (0x14)
> +#define SUNXI_I2C_CCR_DIV_N(val) (val & 0x3)
> +#define SUNXI_I2C_CCR_DIV_M(val) ((val & 0xf) << 3)
> +#define SUNXI_I2C_SRST_REG (0x18)
> +#define SUNXI_I2C_SRST_RESET BIT(0)
> +#define SUNXI_I2C_EFR_REG (0x1c)
> +#define SUNXI_I2C_LCR_REG (0x20)
> +
> +#define SUNXI_I2C_DONE BIT(0)
> +#define SUNXI_I2C_ERROR BIT(1)
> +#define SUNXI_I2C_NAK BIT(2)
> +#define SUNXI_I2C_BUS_ERROR BIT(3)
The register set looks similar to i2c-mv64xxx.c. Has it been considered
to merge the two drivers?
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next prev parent reply other threads:[~2013-06-05 13:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-27 10:00 [PATCHv3 0/6] Add I2C support for Allwinner SoCs Maxime Ripard
[not found] ` <1369648843-1640-1-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2013-05-27 10:00 ` [PATCHv3 1/6] i2c: sunxi: Add Allwinner A1X i2c driver Maxime Ripard
[not found] ` <1369648843-1640-2-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2013-06-05 13:39 ` Wolfram Sang [this message]
2013-06-05 21:31 ` Maxime Ripard
2013-06-10 10:08 ` Maxime Ripard
2013-06-11 18:22 ` Wolfram Sang
2013-06-11 18:21 ` Wolfram Sang
2013-06-12 8:11 ` Maxime Ripard
2013-05-27 10:00 ` [PATCHv3 2/6] ARM: sunxi: dt: Add i2c controller nodes to the DTSI Maxime Ripard
2013-05-27 10:00 ` [PATCHv3 3/6] ARM: sun4i: dt: Add i2c muxing options Maxime Ripard
2013-05-27 10:00 ` [PATCHv3 4/6] ARM: sun5i: " Maxime Ripard
2013-05-27 10:00 ` [PATCHv3 5/6] ARM: sun5i: olinuxino: Enable the i2c controllers Maxime Ripard
2013-05-27 10:00 ` [PATCHv3 6/6] ARM: sun4i: cubieboard: " Maxime Ripard
2013-05-27 19:17 ` [PATCHv3 0/6] Add I2C support for Allwinner SoCs Tomasz Figa
2013-05-29 7:34 ` Maxime Ripard
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