[PATCH 1/4] i2c: rename Blackfin TWI I2C driver to i2c-adi-twi.c

[PATCH 1/4] i2c: rename Blackfin TWI I2C driver to i2c-adi-twi.c

[Sonic Zhang]

From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

Rename twi arch header as well.

Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
---
 arch/blackfin/include/asm/{bfin_twi.h => twi.h}      |  0
 drivers/i2c/busses/Kconfig                           | 14 +++++++-------
 drivers/i2c/busses/Makefile                          |  2 +-
 drivers/i2c/busses/{i2c-bfin-twi.c => i2c-adi-twi.c} |  0
 4 files changed, 8 insertions(+), 8 deletions(-)
 rename arch/blackfin/include/asm/{bfin_twi.h => twi.h} (100%)
 rename drivers/i2c/busses/{i2c-bfin-twi.c => i2c-adi-twi.c} (100%)

diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/twi.h
similarity index 100%
rename from arch/blackfin/include/asm/bfin_twi.h
rename to arch/blackfin/include/asm/twi.h
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 6bcdea5..1ff862f 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -356,19 +356,19 @@ config I2C_BCM_KONA
 
 	  If you do not need KONA I2C inteface, say N.
 
-config I2C_BLACKFIN_TWI
-	tristate "Blackfin TWI I2C support"
+config I2C_ADI_TWI
+	tristate "ADI TWI I2C support"
 	depends on BLACKFIN
 	depends on !BF561 && !BF531 && !BF532 && !BF533
 	help
-	  This is the I2C bus driver for Blackfin on-chip TWI interface.
+	  This is the I2C bus driver for ADI processors' TWI interface.
 
 	  This driver can also be built as a module.  If so, the module
-	  will be called i2c-bfin-twi.
+	  will be called i2c-adi-twi.
 
-config I2C_BLACKFIN_TWI_CLK_KHZ
-	int "Blackfin TWI I2C clock (kHz)"
-	depends on I2C_BLACKFIN_TWI
+config I2C_ADI_TWI_CLK_KHZ
+	int "ADI TWI I2C clock (kHz)"
+	depends on I2C_ADI_TWI
 	range 21 400
 	default 50
 	help
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index a08931f..9bb2e13 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -32,7 +32,7 @@ obj-$(CONFIG_I2C_POWERMAC)	+= i2c-powermac.o
 obj-$(CONFIG_I2C_AT91)		+= i2c-at91.o
 obj-$(CONFIG_I2C_AU1550)	+= i2c-au1550.o
 obj-$(CONFIG_I2C_BCM2835)	+= i2c-bcm2835.o
-obj-$(CONFIG_I2C_BLACKFIN_TWI)	+= i2c-bfin-twi.o
+obj-$(CONFIG_I2C_ADI_TWI)	+= i2c-adi-twi.o
 obj-$(CONFIG_I2C_CBUS_GPIO)	+= i2c-cbus-gpio.o
 obj-$(CONFIG_I2C_CPM)		+= i2c-cpm.o
 obj-$(CONFIG_I2C_DAVINCI)	+= i2c-davinci.o
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-adi-twi.c
similarity index 100%
rename from drivers/i2c/busses/i2c-bfin-twi.c
rename to drivers/i2c/busses/i2c-adi-twi.c
-- 
1.8.2.3

[PATCH 2/4] i2c: i2c-adi: move twi header from arch folder to generic include folder

[Sonic Zhang]

From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
---
 arch/blackfin/include/asm/twi.h | 139 +++-----------------------------------
 include/linux/i2c/i2c-adi.h     | 145 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 153 insertions(+), 131 deletions(-)
 create mode 100644 include/linux/i2c/i2c-adi.h

diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h
index 90c3c00..6f057ee 100644
--- a/arch/blackfin/include/asm/twi.h
+++ b/arch/blackfin/include/asm/twi.h
@@ -1,73 +1,21 @@
 /*
- * bfin_twi.h - interface to Blackfin TWIs
+ * twi.h - TWI register access header
  *
  * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef __ASM_BFIN_TWI_H__
-#define __ASM_BFIN_TWI_H__
+#ifndef __ASM_TWI_H__
+#define __ASM_TWI_H__
 
 #include <linux/types.h>
-#include <linux/i2c.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits.  So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin twi registers layout
- */
-struct bfin_twi_regs {
-	__BFP(clkdiv);
-	__BFP(control);
-	__BFP(slave_ctl);
-	__BFP(slave_stat);
-	__BFP(slave_addr);
-	__BFP(master_ctl);
-	__BFP(master_stat);
-	__BFP(master_addr);
-	__BFP(int_stat);
-	__BFP(int_mask);
-	__BFP(fifo_ctl);
-	__BFP(fifo_stat);
-	u32 __pad[20];
-	__BFP(xmt_data8);
-	__BFP(xmt_data16);
-	__BFP(rcv_data8);
-	__BFP(rcv_data16);
-};
-
-#undef __BFP
-
-struct bfin_twi_iface {
-	int			irq;
-	spinlock_t		lock;
-	char			read_write;
-	u8			command;
-	u8			*transPtr;
-	int			readNum;
-	int			writeNum;
-	int			cur_mode;
-	int			manual_stop;
-	int			result;
-	struct i2c_adapter	adap;
-	struct completion	complete;
-	struct i2c_msg		*pmsg;
-	int			msg_num;
-	int			cur_msg;
-	u16			saved_clkdiv;
-	u16			saved_control;
-	struct bfin_twi_regs __iomem *regs_base;
-};
+#include <asm/blackfin.h>
 
 #define DEFINE_TWI_REG(reg_name, reg) \
-static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
+static inline u16 read_##reg_name(struct adi_twi_iface *iface) \
 	{ return bfin_read16(&iface->regs_base->reg); } \
-static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
+static inline void write_##reg_name(struct adi_twi_iface *iface, u16 v) \
 	{ bfin_write16(&iface->regs_base->reg, v); }
 
 DEFINE_TWI_REG(CLKDIV, clkdiv)
@@ -88,7 +36,7 @@ DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
 DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
 DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
 #else
-static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
+static inline u16 read_RCV_DATA8(struct adi_twi_iface *iface)
 {
 	u16 ret;
 	unsigned long flags;
@@ -100,7 +48,7 @@ static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
 	return ret;
 }
 
-static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
+static inline u16 read_RCV_DATA16(struct adi_twi_iface *iface)
 {
 	u16 ret;
 	unsigned long flags;
@@ -113,75 +61,4 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
 }
 #endif
 
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )				*/
-#define	CLKLOW(x)	((x) & 0xFF)	/* Periods Clock Is Held Low                    */
-#define CLKHI(y)	(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks															*/
-#define	PRESCALE	0x007F	/* SCLKs Per Internal Time Reference (10MHz)    */
-#define	TWI_ENA		0x0080	/* TWI Enable                                                                   */
-#define	SCCB		0x0200	/* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks															*/
-#define	SEN			0x0001	/* Slave Enable                                                                 */
-#define	SADD_LEN	0x0002	/* Slave Address Length                                                 */
-#define	STDVAL		0x0004	/* Slave Transmit Data Valid                                    */
-#define	NAK			0x0008	/* NAK/ACK* Generated At Conclusion Of Transfer */
-#define	GEN			0x0010	/* General Call Address Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks															*/
-#define	SDIR		0x0001	/* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL		0x0002	/* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks													*/
-#define	MEN			0x0001	/* Master Mode Enable                                           */
-#define	MADD_LEN	0x0002	/* Master Address Length                                        */
-#define	MDIR		0x0004	/* Master Transmit Direction (RX/TX*)           */
-#define	FAST		0x0008	/* Use Fast Mode Timing Specs                           */
-#define	STOP		0x0010	/* Issue Stop Condition                                         */
-#define	RSTART		0x0020	/* Repeat Start or Stop* At End Of Transfer     */
-#define	DCNT		0x3FC0	/* Data Bytes To Transfer                                       */
-#define	SDAOVR		0x4000	/* Serial Data Override                                         */
-#define	SCLOVR		0x8000	/* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks														*/
-#define	MPROG		0x0001	/* Master Transfer In Progress                                  */
-#define	LOSTARB		0x0002	/* Lost Arbitration Indicator (Xfer Aborted)    */
-#define	ANAK		0x0004	/* Address Not Acknowledged                                             */
-#define	DNAK		0x0008	/* Data Not Acknowledged                                                */
-#define	BUFRDERR	0x0010	/* Buffer Read Error                                                    */
-#define	BUFWRERR	0x0020	/* Buffer Write Error                                                   */
-#define	SDASEN		0x0040	/* Serial Data Sense                                                    */
-#define	SCLSEN		0x0080	/* Serial Clock Sense                                                   */
-#define	BUSBUSY		0x0100	/* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks						*/
-#define	SINIT		0x0001	/* Slave Transfer Initiated     */
-#define	SCOMP		0x0002	/* Slave Transfer Complete      */
-#define	SERR		0x0004	/* Slave Transfer Error         */
-#define	SOVF		0x0008	/* Slave Overflow                       */
-#define	MCOMP		0x0010	/* Master Transfer Complete     */
-#define	MERR		0x0020	/* Master Transfer Error        */
-#define	XMTSERV		0x0040	/* Transmit FIFO Service        */
-#define	RCVSERV		0x0080	/* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks												*/
-#define	XMTFLUSH	0x0001	/* Transmit Buffer Flush                        */
-#define	RCVFLUSH	0x0002	/* Receive Buffer Flush                         */
-#define	XMTINTLEN	0x0004	/* Transmit Buffer Interrupt Length     */
-#define	RCVINTLEN	0x0008	/* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks															*/
-#define	XMTSTAT		0x0003	/* Transmit FIFO Status                                                 */
-#define	XMT_EMPTY	0x0000	/*              Transmit FIFO Empty                                             */
-#define	XMT_HALF	0x0001	/*              Transmit FIFO Has 1 Byte To Write               */
-#define	XMT_FULL	0x0003	/*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define	RCVSTAT		0x000C	/* Receive FIFO Status                                                  */
-#define	RCV_EMPTY	0x0000	/*              Receive FIFO Empty                                              */
-#define	RCV_HALF	0x0004	/*              Receive FIFO Has 1 Byte To Read                 */
-#define	RCV_FULL	0x000C	/*              Receive FIFO Full (2 Bytes To Read)             */
-
 #endif
diff --git a/include/linux/i2c/i2c-adi.h b/include/linux/i2c/i2c-adi.h
new file mode 100644
index 0000000..28d4e02
--- /dev/null
+++ b/include/linux/i2c/i2c-adi.h
@@ -0,0 +1,145 @@
+/*
+ * i2c_adi.h - interface to ADI TWI controller
+ *
+ * Copyright 2005-2014 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __I2C_ADI_H__
+#define __I2C_ADI_H__
+
+#include <linux/types.h>
+#include <linux/i2c.h>
+
+/*
+ * ADI twi registers layout
+ */
+struct adi_twi_regs {
+	u16 clkdiv;
+	u16 dummy1;
+	u16 control;
+	u16 dummy2;
+	u16 slave_ctl;
+	u16 dummy3;
+	u16 slave_stat;
+	u16 dummy4;
+	u16 slave_addr;
+	u16 dummy5;
+	u16 master_ctl;
+	u16 dummy6;
+	u16 master_stat;
+	u16 dummy7;
+	u16 master_addr;
+	u16 dummy8;
+	u16 int_stat;
+	u16 dummy9;
+	u16 int_mask;
+	u16 dummy10;
+	u16 fifo_ctl;
+	u16 dummy11;
+	u16 fifo_stat;
+	u16 dummy12;
+	u32 __pad[20];
+	u16 xmt_data8;
+	u16 dummy13;
+	u16 xmt_data16;
+	u16 dummy14;
+	u16 rcv_data8;
+	u16 dummy15;
+	u16 rcv_data16;
+	u16 dummy16;
+};
+
+struct adi_twi_iface {
+	int			irq;
+	spinlock_t		lock;
+	char			read_write;
+	u8			command;
+	u8			*transPtr;
+	int			readNum;
+	int			writeNum;
+	int			cur_mode;
+	int			manual_stop;
+	int			result;
+	struct i2c_adapter	adap;
+	struct completion	complete;
+	struct i2c_msg		*pmsg;
+	int			msg_num;
+	int			cur_msg;
+	u16			saved_clkdiv;
+	u16			saved_control;
+	struct adi_twi_regs __iomem *regs_base;
+};
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
+#define	CLKLOW(x)	((x) & 0xFF)	/* Periods Clock Is Held Low */
+#define CLKHI(y)	(((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+
+/* TWI_PRESCALE Masks */
+#define	PRESCALE	0x007F	/* SCLKs Per Internal Time Reference (10MHz) */
+#define	TWI_ENA		0x0080	/* TWI Enable */
+#define	SCCB		0x0200	/* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTL Masks */
+#define	SEN		0x0001	/* Slave Enable */
+#define	SADD_LEN	0x0002	/* Slave Address Length */
+#define	STDVAL		0x0004	/* Slave Transmit Data Valid */
+#define	NAK		0x0008	/* NAK Generated At Conclusion Of Transfer */
+#define	GEN		0x0010	/* General Call Address Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks	*/
+#define	SDIR		0x0001	/* Slave Transfer Direction (RX/TX*) */
+#define GCALL		0x0002	/* General Call Indicator */
+
+/* TWI_MASTER_CTL Masks	*/
+#define	MEN		0x0001	/* Master Mode Enable          */
+#define	MADD_LEN	0x0002	/* Master Address Length       */
+#define	MDIR		0x0004	/* Master Transmit Direction (RX/TX*) */
+#define	FAST		0x0008	/* Use Fast Mode Timing Specs  */
+#define	STOP		0x0010	/* Issue Stop Condition        */
+#define	RSTART		0x0020	/* Repeat Start or Stop* At End Of Transfer */
+#define	DCNT		0x3FC0	/* Data Bytes To Transfer      */
+#define	SDAOVR		0x4000	/* Serial Data Override        */
+#define	SCLOVR		0x8000	/* Serial Clock Override       */
+
+/* TWI_MASTER_STAT Masks */
+#define	MPROG		0x0001	/* Master Transfer In Progress */
+#define	LOSTARB		0x0002	/* Lost Arbitration Indicator (Xfer Aborted) */
+#define	ANAK		0x0004	/* Address Not Acknowledged    */
+#define	DNAK		0x0008	/* Data Not Acknowledged       */
+#define	BUFRDERR	0x0010	/* Buffer Read Error           */
+#define	BUFWRERR	0x0020	/* Buffer Write Error          */
+#define	SDASEN		0x0040	/* Serial Data Sense           */
+#define	SCLSEN		0x0080	/* Serial Clock Sense          */
+#define	BUSBUSY		0x0100	/* Bus Busy Indicator          */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks	*/
+#define	SINIT		0x0001	/* Slave Transfer Initiated    */
+#define	SCOMP		0x0002	/* Slave Transfer Complete     */
+#define	SERR		0x0004	/* Slave Transfer Error        */
+#define	SOVF		0x0008	/* Slave Overflow              */
+#define	MCOMP		0x0010	/* Master Transfer Complete    */
+#define	MERR		0x0020	/* Master Transfer Error       */
+#define	XMTSERV		0x0040	/* Transmit FIFO Service       */
+#define	RCVSERV		0x0080	/* Receive FIFO Service        */
+
+/* TWI_FIFO_CTRL Masks */
+#define	XMTFLUSH	0x0001	/* Transmit Buffer Flush                 */
+#define	RCVFLUSH	0x0002	/* Receive Buffer Flush                  */
+#define	XMTINTLEN	0x0004	/* Transmit Buffer Interrupt Length      */
+#define	RCVINTLEN	0x0008	/* Receive Buffer Interrupt Length       */
+
+/* TWI_FIFO_STAT Masks */
+#define	XMTSTAT		0x0003	/* Transmit FIFO Status                  */
+#define	XMT_EMPTY	0x0000	/* Transmit FIFO Empty                   */
+#define	XMT_HALF	0x0001	/* Transmit FIFO Has 1 Byte To Write     */
+#define	XMT_FULL	0x0003	/* Transmit FIFO Full (2 Bytes To Write) */
+
+#define	RCVSTAT		0x000C	/* Receive FIFO Status                   */
+#define	RCV_EMPTY	0x0000	/* Receive FIFO Empty                    */
+#define	RCV_HALF	0x0004	/* Receive FIFO Has 1 Byte To Read       */
+#define	RCV_FULL	0x000C	/* Receive FIFO Full (2 Bytes To Read)   */
+
+#endif
-- 
1.8.2.3

Re: [PATCH 2/4] i2c: i2c-adi: move twi header from arch folder to generic include folder

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 279 bytes --]

On Sun, Jan 26, 2014 at 03:16:45PM +0800, Sonic Zhang wrote:
> From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
> 
> Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

Any chance to simply include this in the driver?


[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCH 2/4] i2c: i2c-adi: move twi header from arch folder to generic include folder

[Sonic Zhang]

Hi Wolfram,

On Sun, Jan 26, 2014 at 6:29 PM, Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org> wrote:
> On Sun, Jan 26, 2014 at 03:16:45PM +0800, Sonic Zhang wrote:
>> From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
>>
>> Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
>
> Any chance to simply include this in the driver?
>

Yes, it is even better to have it in the driver. I will send a 2nd version.

Thanks,

Sonic

Re: [PATCH 2/4] i2c: i2c-adi: move twi header from arch folder to generic include folder

[Sonic Zhang]

Hi Wolfram,

On Sun, Jan 26, 2014 at 6:29 PM, Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org> wrote:
> On Sun, Jan 26, 2014 at 03:16:45PM +0800, Sonic Zhang wrote:
>> From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
>>
>> Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
>
> Any chance to simply include this in the driver?
>

After more investigation, I found the MMR bits macro and strcuts are
also used in arch/blackfin/kernel/debug-mmrs.c driver. So, I have to
leave them in the individual head file.

Regards,

Sonic

[PATCH 3/4] i2c: i2c-adi: replace blackfin string with adi in ADI TWI driver

[Sonic Zhang]

From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

remove unnecessary SSYNC from the driver
move necessary SSYNC into MMR access functions.
rename i2c-bfin-twi to i2c-adi-twi in file MAINTAINERS

Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
---
 MAINTAINERS                      |   2 +-
 arch/blackfin/include/asm/twi.h  |  23 ++++++-
 drivers/i2c/busses/i2c-adi-twi.c | 128 +++++++++++++++++----------------------
 3 files changed, 78 insertions(+), 75 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1912139..0d01172 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1786,7 +1786,7 @@ M:	Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
 L:	uclinux-dist-devel-ZG0+EudsQA8dtHy/vicBwGD2FQJk+8+b@public.gmane.org
 W:	http://blackfin.uclinux.org/
 S:	Supported
-F:	drivers/i2c/busses/i2c-bfin-twi.c
+F:	drivers/i2c/busses/i2c-adi-twi.c
 
 BLACKFIN MEDIA DRIVER
 M:	Scott Jiang <scott.jiang.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h
index 6f057ee..2cd47e9 100644
--- a/arch/blackfin/include/asm/twi.h
+++ b/arch/blackfin/include/asm/twi.h
@@ -19,7 +19,6 @@ static inline void write_##reg_name(struct adi_twi_iface *iface, u16 v) \
 	{ bfin_write16(&iface->regs_base->reg, v); }
 
 DEFINE_TWI_REG(CLKDIV, clkdiv)
-DEFINE_TWI_REG(CONTROL, control)
 DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
 DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
 DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
@@ -28,7 +27,6 @@ DEFINE_TWI_REG(MASTER_STAT, master_stat)
 DEFINE_TWI_REG(MASTER_ADDR, master_addr)
 DEFINE_TWI_REG(INT_STAT, int_stat)
 DEFINE_TWI_REG(INT_MASK, int_mask)
-DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
 DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
 DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
 DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
@@ -61,4 +59,25 @@ static inline u16 read_RCV_DATA16(struct adi_twi_iface *iface)
 }
 #endif
 
+static inline u16 read_FIFO_CTL(struct adi_twi_iface *iface)
+{
+	return bfin_read16(&iface->regs_base->fifo_ctl);
+}
+
+static inline void write_FIFO_CTL(struct adi_twi_iface *iface, u16 v)
+{
+	bfin_write16(&iface->regs_base->fifo_ctl, v);
+	SSYNC();
+}
+
+static inline u16 read_CONTROL(struct adi_twi_iface *iface)
+{
+	return bfin_read16(&iface->regs_base->control);
+}
+
+static inline void write_CONTROL(struct adi_twi_iface *iface, u16 v)
+{
+	SSYNC();
+	bfin_write16(&iface->regs_base->control, v);
+}
 #endif
diff --git a/drivers/i2c/busses/i2c-adi-twi.c b/drivers/i2c/busses/i2c-adi-twi.c
index 3b9bd9a..9076943 100644
--- a/drivers/i2c/busses/i2c-adi-twi.c
+++ b/drivers/i2c/busses/i2c-adi-twi.c
@@ -1,10 +1,8 @@
 /*
- * Blackfin On-Chip Two Wire Interface Driver
+ * ADI on-chip Two Wire Interface Driver
  *
  * Copyright 2005-2007 Analog Devices Inc.
  *
- * Enter bugs at http://blackfin.uclinux.org/
- *
  * Licensed under the GPL-2 or later.
  */
 
@@ -21,11 +19,11 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/i2c/i2c-adi.h>
 
-#include <asm/blackfin.h>
 #include <asm/portmux.h>
 #include <asm/irq.h>
-#include <asm/bfin_twi.h>
+#include <asm/twi.h>
 
 /* SMBus mode*/
 #define TWI_I2C_MODE_STANDARD		1
@@ -33,7 +31,7 @@
 #define TWI_I2C_MODE_COMBINED		3
 #define TWI_I2C_MODE_REPEAT		4
 
-static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
+static void adi_twi_handle_interrupt(struct adi_twi_iface *iface,
 					unsigned short twi_int_status)
 {
 	unsigned short mast_stat = read_MASTER_STAT(iface);
@@ -65,7 +63,6 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
 		/* Transmit next data */
 		while (iface->writeNum > 0 &&
 			(read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) {
-			SSYNC();
 			write_XMT_DATA8(iface, *(iface->transPtr++));
 			iface->writeNum--;
 		}
@@ -234,9 +231,9 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
 }
 
 /* Interrupt handler */
-static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
+static irqreturn_t adi_twi_interrupt_entry(int irq, void *dev_id)
 {
-	struct bfin_twi_iface *iface = dev_id;
+	struct adi_twi_iface *iface = dev_id;
 	unsigned long flags;
 	unsigned short twi_int_status;
 
@@ -247,8 +244,7 @@ static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 			break;
 		/* Clear interrupt status */
 		write_INT_STAT(iface, twi_int_status);
-		bfin_twi_handle_interrupt(iface, twi_int_status);
-		SSYNC();
+		adi_twi_handle_interrupt(iface, twi_int_status);
 	}
 	spin_unlock_irqrestore(&iface->lock, flags);
 	return IRQ_HANDLED;
@@ -257,10 +253,10 @@ static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 /*
  * One i2c master transfer
  */
-static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
+static int adi_twi_do_master_xfer(struct i2c_adapter *adap,
 				struct i2c_msg *msgs, int num)
 {
-	struct bfin_twi_iface *iface = adap->algo_data;
+	struct adi_twi_iface *iface = adap->algo_data;
 	struct i2c_msg *pmsg;
 	int rc = 0;
 
@@ -294,9 +290,7 @@ static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 	 *  discarded before start a new operation.
 	 */
 	write_FIFO_CTL(iface, 0x3);
-	SSYNC();
 	write_FIFO_CTL(iface, 0);
-	SSYNC();
 
 	if (pmsg->flags & I2C_M_RD)
 		iface->read_write = I2C_SMBUS_READ;
@@ -306,7 +300,6 @@ static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 		if (iface->writeNum > 0) {
 			write_XMT_DATA8(iface, *(iface->transPtr++));
 			iface->writeNum--;
-			SSYNC();
 		}
 	}
 
@@ -315,7 +308,6 @@ static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 
 	/* Interrupt mask . Enable XMT, RCV interrupt */
 	write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
-	SSYNC();
 
 	if (pmsg->len <= 255)
 		write_MASTER_CTL(iface, pmsg->len << 6);
@@ -328,8 +320,7 @@ static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 	write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 		(iface->msg_num > 1 ? RSTART : 0) |
 		((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
-		((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
-	SSYNC();
+		((CONFIG_I2C_ADI_TWI_CLK_KHZ > 100) ? FAST : 0));
 
 	while (!iface->result) {
 		if (!wait_for_completion_timeout(&iface->complete,
@@ -350,20 +341,20 @@ static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 /*
  * Generic i2c master transfer entrypoint
  */
-static int bfin_twi_master_xfer(struct i2c_adapter *adap,
+static int adi_twi_master_xfer(struct i2c_adapter *adap,
 				struct i2c_msg *msgs, int num)
 {
-	return bfin_twi_do_master_xfer(adap, msgs, num);
+	return adi_twi_do_master_xfer(adap, msgs, num);
 }
 
 /*
  * One I2C SMBus transfer
  */
-int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
+int adi_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 			unsigned short flags, char read_write,
 			u8 command, int size, union i2c_smbus_data *data)
 {
-	struct bfin_twi_iface *iface = adap->algo_data;
+	struct adi_twi_iface *iface = adap->algo_data;
 	int rc = 0;
 
 	if (!(read_CONTROL(iface) & TWI_ENA))
@@ -453,7 +444,6 @@ int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 	 * start a new operation.
 	 */
 	write_FIFO_CTL(iface, 0x3);
-	SSYNC();
 	write_FIFO_CTL(iface, 0);
 
 	/* clear int stat */
@@ -461,7 +451,6 @@ int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 
 	/* Set Transmit device address */
 	write_MASTER_ADDR(iface, addr);
-	SSYNC();
 
 	switch (iface->cur_mode) {
 	case TWI_I2C_MODE_STANDARDSUB:
@@ -469,7 +458,6 @@ int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 		write_INT_MASK(iface, MCOMP | MERR |
 			((iface->read_write == I2C_SMBUS_READ) ?
 			RCVSERV : XMTSERV));
-		SSYNC();
 
 		if (iface->writeNum + 1 <= 255)
 			write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
@@ -479,12 +467,11 @@ int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 		}
 		/* Master enable */
 		write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
-			((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
+			((CONFIG_I2C_ADI_TWI_CLK_KHZ>100) ? FAST : 0));
 		break;
 	case TWI_I2C_MODE_COMBINED:
 		write_XMT_DATA8(iface, iface->command);
 		write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
-		SSYNC();
 
 		if (iface->writeNum > 0)
 			write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
@@ -492,7 +479,7 @@ int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 			write_MASTER_CTL(iface, 0x1 << 6);
 		/* Master enable */
 		write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
-			((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
+			((CONFIG_I2C_ADI_TWI_CLK_KHZ>100) ? FAST : 0));
 		break;
 	default:
 		write_MASTER_CTL(iface, 0);
@@ -531,15 +518,13 @@ int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 		write_INT_MASK(iface, MCOMP | MERR |
 			((iface->read_write == I2C_SMBUS_READ) ?
 			RCVSERV : XMTSERV));
-		SSYNC();
 
 		/* Master enable */
 		write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 			((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
-			((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
+			((CONFIG_I2C_ADI_TWI_CLK_KHZ > 100) ? FAST : 0));
 		break;
 	}
-	SSYNC();
 
 	while (!iface->result) {
 		if (!wait_for_completion_timeout(&iface->complete,
@@ -557,18 +542,18 @@ int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 /*
  * Generic I2C SMBus transfer entrypoint
  */
-int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
+int adi_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 			unsigned short flags, char read_write,
 			u8 command, int size, union i2c_smbus_data *data)
 {
-	return bfin_twi_do_smbus_xfer(adap, addr, flags,
+	return adi_twi_do_smbus_xfer(adap, addr, flags,
 			read_write, command, size, data);
 }
 
 /*
  * Return what the adapter supports
  */
-static u32 bfin_twi_functionality(struct i2c_adapter *adap)
+static u32 adi_twi_functionality(struct i2c_adapter *adap)
 {
 	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 	       I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
@@ -576,16 +561,16 @@ static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 	       I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 }
 
-static struct i2c_algorithm bfin_twi_algorithm = {
-	.master_xfer   = bfin_twi_master_xfer,
-	.smbus_xfer    = bfin_twi_smbus_xfer,
-	.functionality = bfin_twi_functionality,
+static struct i2c_algorithm adi_twi_algorithm = {
+	.master_xfer   = adi_twi_master_xfer,
+	.smbus_xfer    = adi_twi_smbus_xfer,
+	.functionality = adi_twi_functionality,
 };
 
 #ifdef CONFIG_PM_SLEEP
-static int i2c_bfin_twi_suspend(struct device *dev)
+static int i2c_adi_twi_suspend(struct device *dev)
 {
-	struct bfin_twi_iface *iface = dev_get_drvdata(dev);
+	struct adi_twi_iface *iface = dev_get_drvdata(dev);
 
 	iface->saved_clkdiv = read_CLKDIV(iface);
 	iface->saved_control = read_CONTROL(iface);
@@ -598,11 +583,11 @@ static int i2c_bfin_twi_suspend(struct device *dev)
 	return 0;
 }
 
-static int i2c_bfin_twi_resume(struct device *dev)
+static int i2c_adi_twi_resume(struct device *dev)
 {
-	struct bfin_twi_iface *iface = dev_get_drvdata(dev);
+	struct adi_twi_iface *iface = dev_get_drvdata(dev);
 
-	int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
+	int rc = request_irq(iface->irq, adi_twi_interrupt_entry,
 		0, to_platform_device(dev)->name, iface);
 	if (rc) {
 		dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
@@ -618,22 +603,22 @@ static int i2c_bfin_twi_resume(struct device *dev)
 	return 0;
 }
 
-static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
-			 i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
-#define I2C_BFIN_TWI_PM_OPS	(&i2c_bfin_twi_pm)
+static SIMPLE_DEV_PM_OPS(i2c_adi_twi_pm,
+			 i2c_adi_twi_suspend, i2c_adi_twi_resume);
+#define I2C_ADI_TWI_PM_OPS    (&i2c_adi_twi_pm)
 #else
-#define I2C_BFIN_TWI_PM_OPS	NULL
+#define I2C_ADI_TWI_PM_OPS    NULL
 #endif
 
-static int i2c_bfin_twi_probe(struct platform_device *pdev)
+static int i2c_adi_twi_probe(struct platform_device *pdev)
 {
-	struct bfin_twi_iface *iface;
+	struct adi_twi_iface *iface;
 	struct i2c_adapter *p_adap;
 	struct resource *res;
 	int rc;
 	unsigned int clkhilow;
 
-	iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
+	iface = kzalloc(sizeof(struct adi_twi_iface), GFP_KERNEL);
 	if (!iface) {
 		dev_err(&pdev->dev, "Cannot allocate memory\n");
 		rc = -ENOMEM;
@@ -667,7 +652,7 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
 	p_adap = &iface->adap;
 	p_adap->nr = pdev->id;
 	strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
-	p_adap->algo = &bfin_twi_algorithm;
+	p_adap->algo = &adi_twi_algorithm;
 	p_adap->algo_data = iface;
 	p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 	p_adap->dev.parent = &pdev->dev;
@@ -676,13 +661,13 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
 
 	rc = peripheral_request_list(
 			dev_get_platdata(&pdev->dev),
-			"i2c-bfin-twi");
+			"i2c-adi-twi");
 	if (rc) {
 		dev_err(&pdev->dev, "Can't setup pin mux!\n");
 		goto out_error_pin_mux;
 	}
 
-	rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
+	rc = request_irq(iface->irq, adi_twi_interrupt_entry,
 		0, pdev->name, iface);
 	if (rc) {
 		dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
@@ -697,14 +682,13 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
 	 * We will not end up with a CLKDIV=0 because no one will specify
 	 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 	 */
-	clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
+	clkhilow = ((10 * 1000 / CONFIG_I2C_ADI_TWI_CLK_KHZ) + 1) / 2;
 
 	/* Set Twi interface clock as specified */
 	write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 
 	/* Enable TWI */
 	write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
-	SSYNC();
 
 	rc = i2c_add_numbered_adapter(p_adap);
 	if (rc < 0) {
@@ -714,7 +698,7 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, iface);
 
-	dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
+	dev_info(&pdev->dev, "ADI on-chip I2C TWI Contoller, "
 		"regs_base@%p\n", iface->regs_base);
 
 	return 0;
@@ -733,9 +717,9 @@ out_error_nomem:
 	return rc;
 }
 
-static int i2c_bfin_twi_remove(struct platform_device *pdev)
+static int i2c_adi_twi_remove(struct platform_device *pdev)
 {
-	struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
+	struct adi_twi_iface *iface = platform_get_drvdata(pdev);
 
 	i2c_del_adapter(&(iface->adap));
 	free_irq(iface->irq, iface);
@@ -746,30 +730,30 @@ static int i2c_bfin_twi_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static struct platform_driver i2c_bfin_twi_driver = {
-	.probe		= i2c_bfin_twi_probe,
-	.remove		= i2c_bfin_twi_remove,
+static struct platform_driver i2c_adi_twi_driver = {
+	.probe		= i2c_adi_twi_probe,
+	.remove		= i2c_adi_twi_remove,
 	.driver		= {
-		.name	= "i2c-bfin-twi",
+		.name	= "i2c-adi-twi",
 		.owner	= THIS_MODULE,
-		.pm	= I2C_BFIN_TWI_PM_OPS,
+		.pm	= I2C_ADI_TWI_PM_OPS,
 	},
 };
 
-static int __init i2c_bfin_twi_init(void)
+static int __init i2c_adi_twi_init(void)
 {
-	return platform_driver_register(&i2c_bfin_twi_driver);
+	return platform_driver_register(&i2c_adi_twi_driver);
 }
 
-static void __exit i2c_bfin_twi_exit(void)
+static void __exit i2c_adi_twi_exit(void)
 {
-	platform_driver_unregister(&i2c_bfin_twi_driver);
+	platform_driver_unregister(&i2c_adi_twi_driver);
 }
 
-subsys_initcall(i2c_bfin_twi_init);
-module_exit(i2c_bfin_twi_exit);
+subsys_initcall(i2c_adi_twi_init);
+module_exit(i2c_adi_twi_exit);
 
 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
-MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
+MODULE_DESCRIPTION("ADI on-chip I2C TWI Contoller Driver");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:i2c-bfin-twi");
+MODULE_ALIAS("platform:i2c-adi-twi");
-- 
1.8.2.3

[PATCH 4/4] video: Update dependant blackfin i2c driver name string

[Sonic Zhang]

From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

rename i2c bus driver name i2c-bfin-twi to i2c-adi-twi
rename I2C_BLACKFIN_TWI with I2C_ADI_TWI in framebuffer driver config options

Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
---
 drivers/video/Kconfig          | 2 +-
 drivers/video/bf537-lq035.c    | 2 +-
 drivers/video/bfin_adv7393fb.c | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 22262a3..18d44b5 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -614,7 +614,7 @@ config FB_BFIN_LQ035Q1
 
 config FB_BF537_LQ035
 	tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
-	depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
+	depends on FB && (BF534 || BF536 || BF537) && I2C_ADI_TWI
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/bf537-lq035.c b/drivers/video/bf537-lq035.c
index a82d257..e934491 100644
--- a/drivers/video/bf537-lq035.c
+++ b/drivers/video/bf537-lq035.c
@@ -900,7 +900,7 @@ static struct platform_driver bfin_lq035_driver = {
 
 static int __init bfin_lq035_driver_init(void)
 {
-	request_module("i2c-bfin-twi");
+	request_module("i2c-adi-twi");
 	return platform_driver_register(&bfin_lq035_driver);
 }
 module_init(bfin_lq035_driver_init);
diff --git a/drivers/video/bfin_adv7393fb.c b/drivers/video/bfin_adv7393fb.c
index a54f7f7..4664343 100644
--- a/drivers/video/bfin_adv7393fb.c
+++ b/drivers/video/bfin_adv7393fb.c
@@ -795,8 +795,8 @@ static struct i2c_driver bfin_adv7393_fb_driver = {
 
 static int __init bfin_adv7393_fb_driver_init(void)
 {
-#if  defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
-	request_module("i2c-bfin-twi");
+#if IS_ENABLED(CONFIG_I2C_ADI_TWI)
+	request_module("i2c-adi-twi");
 #else
 	request_module("i2c-gpio");
 #endif
-- 
1.8.2.3

Re: [PATCH 1/4] i2c: rename Blackfin TWI I2C driver to i2c-adi-twi.c

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 498 bytes --]

On Sun, Jan 26, 2014 at 03:16:44PM +0800, Sonic Zhang wrote:
> From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
> 
> Rename twi arch header as well.

You describe what you do, yet the commit message should describe WHY the
change is needed. This applies for the other patches as well.

> 
> Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

What is the difference between the two versions you sent? Please always
describe that.


[-- Attachment #2: Digital signature --]
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Re: [PATCH 1/4] i2c: rename Blackfin TWI I2C driver to i2c-adi-twi.c

[Sonic Zhang]

Hi Wolfram,

On Sun, Jan 26, 2014 at 6:28 PM, Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org> wrote:
> On Sun, Jan 26, 2014 at 03:16:44PM +0800, Sonic Zhang wrote:
>> From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
>>
>> Rename twi arch header as well.
>
> You describe what you do, yet the commit message should describe WHY the
> change is needed. This applies for the other patches as well.

OK, I will add WHY in 2nd version. The ADI TWI peripheral is not
binding to the Blackfin processor only. It is better to use a more
generic name for this driver.

>
>>
>> Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
>
> What is the difference between the two versions you sent? Please always
> describe that.
>

Sorry for the confusion. I didn't receive the first patch set a short
while after I sent them. So, I sent the same patch set again. I should
be more patient.

Thanks

Sonic

Re: [PATCH 1/4] i2c: rename Blackfin TWI I2C driver to i2c-adi-twi.c

[Wolfram Sang]

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> > You describe what you do, yet the commit message should describe WHY the
> > change is needed. This applies for the other patches as well.
> 
> OK, I will add WHY in 2nd version. The ADI TWI peripheral is not
> binding to the Blackfin processor only. It is better to use a more
> generic name for this driver.

Oh, this is the only reason? Then NACK. Names always change, even
company names. Trying to keep that up-to-date only creates lots of
changes for no technical gain. It is quite common that drivers keep the
name of their first incarnation.

Thanks,

   Wolfram


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Re: [PATCH 1/4] i2c: rename Blackfin TWI I2C driver to i2c-adi-twi.c

[Sonic Zhang]

Hi Wolfram,

On Mon, Jan 27, 2014 at 5:28 PM, Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org> wrote:
>
>> > You describe what you do, yet the commit message should describe WHY the
>> > change is needed. This applies for the other patches as well.
>>
>> OK, I will add WHY in 2nd version. The ADI TWI peripheral is not
>> binding to the Blackfin processor only. It is better to use a more
>> generic name for this driver.
>
> Oh, this is the only reason? Then NACK. Names always change, even
> company names. Trying to keep that up-to-date only creates lots of
> changes for no technical gain. It is quite common that drivers keep the
> name of their first incarnation.

This is part of the reason. The other reason is some macro such as
SSYNC is blackfin specific. So, all must have SSYNC should be moved
into the architecture code.

Regards,

Sonic

Re: [PATCH 1/4] i2c: rename Blackfin TWI I2C driver to i2c-adi-twi.c

[Wolfram Sang]

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> This is part of the reason. The other reason is some macro such as
> SSYNC is blackfin specific. So, all must have SSYNC should be moved
> into the architecture code.

Ah, yes, ACK for moving arch specific parts out of the driver! Please
submit this part of the changes.


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[PATCH 1/4] i2c: rename Blackfin TWI I2C driver to i2c-adi-twi.c

[Sonic Zhang]

From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

Rename twi arch header as well.

Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
---
 arch/blackfin/include/asm/{bfin_twi.h => twi.h}      |  0
 drivers/i2c/busses/Kconfig                           | 14 +++++++-------
 drivers/i2c/busses/Makefile                          |  2 +-
 drivers/i2c/busses/{i2c-bfin-twi.c => i2c-adi-twi.c} |  0
 4 files changed, 8 insertions(+), 8 deletions(-)
 rename arch/blackfin/include/asm/{bfin_twi.h => twi.h} (100%)
 rename drivers/i2c/busses/{i2c-bfin-twi.c => i2c-adi-twi.c} (100%)

diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/twi.h
similarity index 100%
rename from arch/blackfin/include/asm/bfin_twi.h
rename to arch/blackfin/include/asm/twi.h
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 6bcdea5..1ff862f 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -356,19 +356,19 @@ config I2C_BCM_KONA
 
 	  If you do not need KONA I2C inteface, say N.
 
-config I2C_BLACKFIN_TWI
-	tristate "Blackfin TWI I2C support"
+config I2C_ADI_TWI
+	tristate "ADI TWI I2C support"
 	depends on BLACKFIN
 	depends on !BF561 && !BF531 && !BF532 && !BF533
 	help
-	  This is the I2C bus driver for Blackfin on-chip TWI interface.
+	  This is the I2C bus driver for ADI processors' TWI interface.
 
 	  This driver can also be built as a module.  If so, the module
-	  will be called i2c-bfin-twi.
+	  will be called i2c-adi-twi.
 
-config I2C_BLACKFIN_TWI_CLK_KHZ
-	int "Blackfin TWI I2C clock (kHz)"
-	depends on I2C_BLACKFIN_TWI
+config I2C_ADI_TWI_CLK_KHZ
+	int "ADI TWI I2C clock (kHz)"
+	depends on I2C_ADI_TWI
 	range 21 400
 	default 50
 	help
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index a08931f..9bb2e13 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -32,7 +32,7 @@ obj-$(CONFIG_I2C_POWERMAC)	+= i2c-powermac.o
 obj-$(CONFIG_I2C_AT91)		+= i2c-at91.o
 obj-$(CONFIG_I2C_AU1550)	+= i2c-au1550.o
 obj-$(CONFIG_I2C_BCM2835)	+= i2c-bcm2835.o
-obj-$(CONFIG_I2C_BLACKFIN_TWI)	+= i2c-bfin-twi.o
+obj-$(CONFIG_I2C_ADI_TWI)	+= i2c-adi-twi.o
 obj-$(CONFIG_I2C_CBUS_GPIO)	+= i2c-cbus-gpio.o
 obj-$(CONFIG_I2C_CPM)		+= i2c-cpm.o
 obj-$(CONFIG_I2C_DAVINCI)	+= i2c-davinci.o
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-adi-twi.c
similarity index 100%
rename from drivers/i2c/busses/i2c-bfin-twi.c
rename to drivers/i2c/busses/i2c-adi-twi.c
-- 
1.8.2.3

[PATCH 2/4] i2c: i2c-adi: move twi header from arch folder to generic include folder

[Sonic Zhang]

From: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

Signed-off-by: Sonic Zhang <sonic.zhang-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
---
 arch/blackfin/include/asm/twi.h | 139 +++-----------------------------------
 include/linux/i2c/i2c-adi.h     | 145 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 153 insertions(+), 131 deletions(-)
 create mode 100644 include/linux/i2c/i2c-adi.h

diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h
index 90c3c00..6f057ee 100644
--- a/arch/blackfin/include/asm/twi.h
+++ b/arch/blackfin/include/asm/twi.h
@@ -1,73 +1,21 @@
 /*
- * bfin_twi.h - interface to Blackfin TWIs
+ * twi.h - TWI register access header
  *
  * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef __ASM_BFIN_TWI_H__
-#define __ASM_BFIN_TWI_H__
+#ifndef __ASM_TWI_H__
+#define __ASM_TWI_H__
 
 #include <linux/types.h>
-#include <linux/i2c.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits.  So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin twi registers layout
- */
-struct bfin_twi_regs {
-	__BFP(clkdiv);
-	__BFP(control);
-	__BFP(slave_ctl);
-	__BFP(slave_stat);
-	__BFP(slave_addr);
-	__BFP(master_ctl);
-	__BFP(master_stat);
-	__BFP(master_addr);
-	__BFP(int_stat);
-	__BFP(int_mask);
-	__BFP(fifo_ctl);
-	__BFP(fifo_stat);
-	u32 __pad[20];
-	__BFP(xmt_data8);
-	__BFP(xmt_data16);
-	__BFP(rcv_data8);
-	__BFP(rcv_data16);
-};
-
-#undef __BFP
-
-struct bfin_twi_iface {
-	int			irq;
-	spinlock_t		lock;
-	char			read_write;
-	u8			command;
-	u8			*transPtr;
-	int			readNum;
-	int			writeNum;
-	int			cur_mode;
-	int			manual_stop;
-	int			result;
-	struct i2c_adapter	adap;
-	struct completion	complete;
-	struct i2c_msg		*pmsg;
-	int			msg_num;
-	int			cur_msg;
-	u16			saved_clkdiv;
-	u16			saved_control;
-	struct bfin_twi_regs __iomem *regs_base;
-};
+#include <asm/blackfin.h>
 
 #define DEFINE_TWI_REG(reg_name, reg) \
-static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
+static inline u16 read_##reg_name(struct adi_twi_iface *iface) \
 	{ return bfin_read16(&iface->regs_base->reg); } \
-static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
+static inline void write_##reg_name(struct adi_twi_iface *iface, u16 v) \
 	{ bfin_write16(&iface->regs_base->reg, v); }
 
 DEFINE_TWI_REG(CLKDIV, clkdiv)
@@ -88,7 +36,7 @@ DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
 DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
 DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
 #else
-static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
+static inline u16 read_RCV_DATA8(struct adi_twi_iface *iface)
 {
 	u16 ret;
 	unsigned long flags;
@@ -100,7 +48,7 @@ static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
 	return ret;
 }
 
-static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
+static inline u16 read_RCV_DATA16(struct adi_twi_iface *iface)
 {
 	u16 ret;
 	unsigned long flags;
@@ -113,75 +61,4 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
 }
 #endif
 
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )				*/
-#define	CLKLOW(x)	((x) & 0xFF)	/* Periods Clock Is Held Low                    */
-#define CLKHI(y)	(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks															*/
-#define	PRESCALE	0x007F	/* SCLKs Per Internal Time Reference (10MHz)    */
-#define	TWI_ENA		0x0080	/* TWI Enable                                                                   */
-#define	SCCB		0x0200	/* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks															*/
-#define	SEN			0x0001	/* Slave Enable                                                                 */
-#define	SADD_LEN	0x0002	/* Slave Address Length                                                 */
-#define	STDVAL		0x0004	/* Slave Transmit Data Valid                                    */
-#define	NAK			0x0008	/* NAK/ACK* Generated At Conclusion Of Transfer */
-#define	GEN			0x0010	/* General Call Address Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks															*/
-#define	SDIR		0x0001	/* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL		0x0002	/* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks													*/
-#define	MEN			0x0001	/* Master Mode Enable                                           */
-#define	MADD_LEN	0x0002	/* Master Address Length                                        */
-#define	MDIR		0x0004	/* Master Transmit Direction (RX/TX*)           */
-#define	FAST		0x0008	/* Use Fast Mode Timing Specs                           */
-#define	STOP		0x0010	/* Issue Stop Condition                                         */
-#define	RSTART		0x0020	/* Repeat Start or Stop* At End Of Transfer     */
-#define	DCNT		0x3FC0	/* Data Bytes To Transfer                                       */
-#define	SDAOVR		0x4000	/* Serial Data Override                                         */
-#define	SCLOVR		0x8000	/* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks														*/
-#define	MPROG		0x0001	/* Master Transfer In Progress                                  */
-#define	LOSTARB		0x0002	/* Lost Arbitration Indicator (Xfer Aborted)    */
-#define	ANAK		0x0004	/* Address Not Acknowledged                                             */
-#define	DNAK		0x0008	/* Data Not Acknowledged                                                */
-#define	BUFRDERR	0x0010	/* Buffer Read Error                                                    */
-#define	BUFWRERR	0x0020	/* Buffer Write Error                                                   */
-#define	SDASEN		0x0040	/* Serial Data Sense                                                    */
-#define	SCLSEN		0x0080	/* Serial Clock Sense                                                   */
-#define	BUSBUSY		0x0100	/* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks						*/
-#define	SINIT		0x0001	/* Slave Transfer Initiated     */
-#define	SCOMP		0x0002	/* Slave Transfer Complete      */
-#define	SERR		0x0004	/* Slave Transfer Error         */
-#define	SOVF		0x0008	/* Slave Overflow                       */
-#define	MCOMP		0x0010	/* Master Transfer Complete     */
-#define	MERR		0x0020	/* Master Transfer Error        */
-#define	XMTSERV		0x0040	/* Transmit FIFO Service        */
-#define	RCVSERV		0x0080	/* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks												*/
-#define	XMTFLUSH	0x0001	/* Transmit Buffer Flush                        */
-#define	RCVFLUSH	0x0002	/* Receive Buffer Flush                         */
-#define	XMTINTLEN	0x0004	/* Transmit Buffer Interrupt Length     */
-#define	RCVINTLEN	0x0008	/* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks															*/
-#define	XMTSTAT		0x0003	/* Transmit FIFO Status                                                 */
-#define	XMT_EMPTY	0x0000	/*              Transmit FIFO Empty                                             */
-#define	XMT_HALF	0x0001	/*              Transmit FIFO Has 1 Byte To Write               */
-#define	XMT_FULL	0x0003	/*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define	RCVSTAT		0x000C	/* Receive FIFO Status                                                  */
-#define	RCV_EMPTY	0x0000	/*              Receive FIFO Empty                                              */
-#define	RCV_HALF	0x0004	/*              Receive FIFO Has 1 Byte To Read                 */
-#define	RCV_FULL	0x000C	/*              Receive FIFO Full (2 Bytes To Read)             */
-
 #endif
diff --git a/include/linux/i2c/i2c-adi.h b/include/linux/i2c/i2c-adi.h
new file mode 100644
index 0000000..28d4e02
--- /dev/null
+++ b/include/linux/i2c/i2c-adi.h
@@ -0,0 +1,145 @@
+/*
+ * i2c_adi.h - interface to ADI TWI controller
+ *
+ * Copyright 2005-2014 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __I2C_ADI_H__
+#define __I2C_ADI_H__
+
+#include <linux/types.h>
+#include <linux/i2c.h>
+
+/*
+ * ADI twi registers layout
+ */
+struct adi_twi_regs {
+	u16 clkdiv;
+	u16 dummy1;
+	u16 control;
+	u16 dummy2;
+	u16 slave_ctl;
+	u16 dummy3;
+	u16 slave_stat;
+	u16 dummy4;
+	u16 slave_addr;
+	u16 dummy5;
+	u16 master_ctl;
+	u16 dummy6;
+	u16 master_stat;
+	u16 dummy7;
+	u16 master_addr;
+	u16 dummy8;
+	u16 int_stat;
+	u16 dummy9;
+	u16 int_mask;
+	u16 dummy10;
+	u16 fifo_ctl;
+	u16 dummy11;
+	u16 fifo_stat;
+	u16 dummy12;
+	u32 __pad[20];
+	u16 xmt_data8;
+	u16 dummy13;
+	u16 xmt_data16;
+	u16 dummy14;
+	u16 rcv_data8;
+	u16 dummy15;
+	u16 rcv_data16;
+	u16 dummy16;
+};
+
+struct adi_twi_iface {
+	int			irq;
+	spinlock_t		lock;
+	char			read_write;
+	u8			command;
+	u8			*transPtr;
+	int			readNum;
+	int			writeNum;
+	int			cur_mode;
+	int			manual_stop;
+	int			result;
+	struct i2c_adapter	adap;
+	struct completion	complete;
+	struct i2c_msg		*pmsg;
+	int			msg_num;
+	int			cur_msg;
+	u16			saved_clkdiv;
+	u16			saved_control;
+	struct adi_twi_regs __iomem *regs_base;
+};
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
+#define	CLKLOW(x)	((x) & 0xFF)	/* Periods Clock Is Held Low */
+#define CLKHI(y)	(((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+
+/* TWI_PRESCALE Masks */
+#define	PRESCALE	0x007F	/* SCLKs Per Internal Time Reference (10MHz) */
+#define	TWI_ENA		0x0080	/* TWI Enable */
+#define	SCCB		0x0200	/* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTL Masks */
+#define	SEN		0x0001	/* Slave Enable */
+#define	SADD_LEN	0x0002	/* Slave Address Length */
+#define	STDVAL		0x0004	/* Slave Transmit Data Valid */
+#define	NAK		0x0008	/* NAK Generated At Conclusion Of Transfer */
+#define	GEN		0x0010	/* General Call Address Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks	*/
+#define	SDIR		0x0001	/* Slave Transfer Direction (RX/TX*) */
+#define GCALL		0x0002	/* General Call Indicator */
+
+/* TWI_MASTER_CTL Masks	*/
+#define	MEN		0x0001	/* Master Mode Enable          */
+#define	MADD_LEN	0x0002	/* Master Address Length       */
+#define	MDIR		0x0004	/* Master Transmit Direction (RX/TX*) */
+#define	FAST		0x0008	/* Use Fast Mode Timing Specs  */
+#define	STOP		0x0010	/* Issue Stop Condition        */
+#define	RSTART		0x0020	/* Repeat Start or Stop* At End Of Transfer */
+#define	DCNT		0x3FC0	/* Data Bytes To Transfer      */
+#define	SDAOVR		0x4000	/* Serial Data Override        */
+#define	SCLOVR		0x8000	/* Serial Clock Override       */
+
+/* TWI_MASTER_STAT Masks */
+#define	MPROG		0x0001	/* Master Transfer In Progress */
+#define	LOSTARB		0x0002	/* Lost Arbitration Indicator (Xfer Aborted) */
+#define	ANAK		0x0004	/* Address Not Acknowledged    */
+#define	DNAK		0x0008	/* Data Not Acknowledged       */
+#define	BUFRDERR	0x0010	/* Buffer Read Error           */
+#define	BUFWRERR	0x0020	/* Buffer Write Error          */
+#define	SDASEN		0x0040	/* Serial Data Sense           */
+#define	SCLSEN		0x0080	/* Serial Clock Sense          */
+#define	BUSBUSY		0x0100	/* Bus Busy Indicator          */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks	*/
+#define	SINIT		0x0001	/* Slave Transfer Initiated    */
+#define	SCOMP		0x0002	/* Slave Transfer Complete     */
+#define	SERR		0x0004	/* Slave Transfer Error        */
+#define	SOVF		0x0008	/* Slave Overflow              */
+#define	MCOMP		0x0010	/* Master Transfer Complete    */
+#define	MERR		0x0020	/* Master Transfer Error       */
+#define	XMTSERV		0x0040	/* Transmit FIFO Service       */
+#define	RCVSERV		0x0080	/* Receive FIFO Service        */
+
+/* TWI_FIFO_CTRL Masks */
+#define	XMTFLUSH	0x0001	/* Transmit Buffer Flush                 */
+#define	RCVFLUSH	0x0002	/* Receive Buffer Flush                  */
+#define	XMTINTLEN	0x0004	/* Transmit Buffer Interrupt Length      */
+#define	RCVINTLEN	0x0008	/* Receive Buffer Interrupt Length       */
+
+/* TWI_FIFO_STAT Masks */
+#define	XMTSTAT		0x0003	/* Transmit FIFO Status                  */
+#define	XMT_EMPTY	0x0000	/* Transmit FIFO Empty                   */
+#define	XMT_HALF	0x0001	/* Transmit FIFO Has 1 Byte To Write     */
+#define	XMT_FULL	0x0003	/* Transmit FIFO Full (2 Bytes To Write) */
+
+#define	RCVSTAT		0x000C	/* Receive FIFO Status                   */
+#define	RCV_EMPTY	0x0000	/* Receive FIFO Empty                    */
+#define	RCV_HALF	0x0004	/* Receive FIFO Has 1 Byte To Read       */
+#define	RCV_FULL	0x000C	/* Receive FIFO Full (2 Bytes To Read)   */
+
+#endif
-- 
1.8.2.3