From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: Alexander Sverdlin
<alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Cc: Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>,
Kevin Hilman
<khilman-1D3HCaltpLuhEniVeURVKkEOCMrvLtNR@public.gmane.org>,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "Lawnick,
Michael (Nokia - DE/Ulm)"
<michael.lawnick-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH] i2c: davinci: Optimize SCL generation
Date: Wed, 17 Jun 2015 14:45:48 +0200 [thread overview]
Message-ID: <20150617124547.GF13393@katana> (raw)
In-Reply-To: <5579565E.1020908-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
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On Thu, Jun 11, 2015 at 11:35:26AM +0200, Alexander Sverdlin wrote:
> There are several cases where current clock configuration algorithm produces
> not optimal results:
> - truncation in "clk" calculation leads to the fact that actual BUS frequency
> will be always higher than spec except two exact module frequences 8MHz and
> 12MHz in the whole 7-12MHz range of permitted frequences
> - driver configures SCL HIGH to LOW ratio always 1 to 1 and this doesn't work
> well in 400kHz case, namely minimum time of LOW state (according to I2C Spec
> 2.1) 1.3us will not be fulfilled. HIGH to LOW ratio 1 to 2 would be more
> approriate here.
>
> Signed-off-by: Michael Lawnick <michael.lawnick-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
Applied to for-next, thanks!
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prev parent reply other threads:[~2015-06-17 12:45 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-11 9:35 [PATCH] i2c: davinci: Optimize SCL generation Alexander Sverdlin
[not found] ` <5579565E.1020908-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
2015-06-17 12:45 ` Wolfram Sang [this message]
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