Re: [PATCH v3] i2c: omap: improve duty cycle on SCL

[Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>]

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On Thu, Jun 18, 2015 at 12:25:58PM -0500, Felipe Balbi wrote:
> On Thu, Jun 18, 2015 at 10:09:59AM +0200, Alexander Sverdlin wrote:
> > Hello Felipe,
> > 
> > On 17/06/15 21:31, ext Felipe Balbi wrote:
> > > With this patch we try to be as close to 50%
> > > duty cycle as possible. The reason for this
> > > is that some devices present an erratic behavior
> > > with certain duty cycles.
> > > 
> > > One such example is TPS65218 PMIC which fails
> > > to change voltages when running @ 400kHz and
> > > duty cycle is lower than 34%.
> > > 
> > > The idea of the patch is simple:
> > > 
> > > calculate desired scl_period from requested scl
> > > and use 50% for tLow and 50% for tHigh.
> > > 
> > > tLow is calculated with a DIV_ROUND_UP() to make
> > > sure it's slightly higher than tHigh and to make
> > > sure that we end up within I2C specifications.
> > 
> > if you refuse to change the calculations to achieve maximum possible
> > bus rate (as I've shown you with SCLL=9 and SCLH=9), maybe you want to
> > change the description? Because you are doing something else than is
> > written here. You are only in spec because you are not doing 50% duty
> > cycle. And you didn't mention here that you lower the bus speed below
> > 400kHz to achieve this.
> 
> and there's a comment where the calculation goes which states "as close
> to 50% as possible but we make sure tLow is higher than tHigh so we're
> still within spec".

So, is that ready to go in for-next?


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