* [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver.
@ 2016-01-29 1:35 Liguo Zhang
2016-01-29 9:48 ` Daniel Kurtz
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Liguo Zhang @ 2016-01-29 1:35 UTC (permalink / raw)
To: Wolfram Sang
Cc: srv_heupstream, Matthias Brugger, Eddie Huang, Xudong Chen,
Sascha Hauer, linux-i2c, linux-kernel, linux-arm-kernel,
linux-mediatek, Liguo Zhang
If 4GB mode is enable, we should add 4gb mode support in i2c driver.
Set 4GB mode register to support 4GB mode.
Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
---
change in v3:
Only inline the computation of reg_4g_mode in mtk_i2c_set_4g_mode().
change in v2:
Define a static inline funtion mtk_i2c_set_4g_mode() for support 4g mode.
---
drivers/i2c/busses/i2c-mt65xx.c | 42 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index aec8e6c..3c484f0 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -60,6 +60,7 @@
#define I2C_DMA_INT_FLAG_NONE 0x0000
#define I2C_DMA_CLR_FLAG 0x0000
#define I2C_DMA_HARD_RST 0x0002
+#define I2C_DMA_4G_MODE 0x0001
#define I2C_DEFAULT_SPEED 100000 /* hz */
#define MAX_FS_MODE_SPEED 400000
@@ -88,6 +89,8 @@ enum DMA_REGS_OFFSET {
OFFSET_RX_MEM_ADDR = 0x20,
OFFSET_TX_LEN = 0x24,
OFFSET_RX_LEN = 0x28,
+ OFFSET_TX_4G_MODE = 0x54,
+ OFFSET_RX_4G_MODE = 0x58,
};
enum i2c_trans_st_rs {
@@ -133,6 +136,7 @@ struct mtk_i2c_compatible {
unsigned char dcm: 1;
unsigned char auto_restart: 1;
unsigned char aux_len_reg: 1;
+ unsigned char support_33bits: 1;
};
struct mtk_i2c {
@@ -182,6 +186,7 @@ static const struct mtk_i2c_compatible mt6577_compat = {
.dcm = 1,
.auto_restart = 0,
.aux_len_reg = 0,
+ .support_33bits = 0,
};
static const struct mtk_i2c_compatible mt6589_compat = {
@@ -190,6 +195,7 @@ static const struct mtk_i2c_compatible mt6589_compat = {
.dcm = 0,
.auto_restart = 0,
.aux_len_reg = 0,
+ .support_33bits = 0,
};
static const struct mtk_i2c_compatible mt8173_compat = {
@@ -198,6 +204,7 @@ static const struct mtk_i2c_compatible mt8173_compat = {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
+ .support_33bits = 1,
};
static const struct of_device_id mtk_i2c_of_match[] = {
@@ -366,6 +373,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
return 0;
}
+static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
+{
+ return (addr & BIT(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
+}
+
static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
int num, int left_num)
{
@@ -373,6 +385,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
u16 start_reg;
u16 control_reg;
u16 restart_flag = 0;
+ u32 reg_4g_mode = 0;
dma_addr_t rpaddr = 0;
dma_addr_t wpaddr = 0;
int ret;
@@ -439,6 +452,12 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
msgs->len, DMA_FROM_DEVICE);
if (dma_mapping_error(i2c->dev, rpaddr))
return -ENOMEM;
+
+ if (i2c->dev_comp->support_33bits) {
+ reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+ writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
+ }
+
writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
} else if (i2c->op == I2C_MASTER_WR) {
@@ -448,6 +467,12 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
msgs->len, DMA_TO_DEVICE);
if (dma_mapping_error(i2c->dev, wpaddr))
return -ENOMEM;
+
+ if (i2c->dev_comp->support_33bits) {
+ reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+ writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
+ }
+
writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
} else {
@@ -465,6 +490,15 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
msgs->len, DMA_TO_DEVICE);
return -ENOMEM;
}
+
+ if (i2c->dev_comp->support_33bits) {
+ reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+ writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
+
+ reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+ writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
+ }
+
writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
@@ -729,6 +763,14 @@ static int mtk_i2c_probe(struct platform_device *pdev)
return -EINVAL;
}
+ if (i2c->dev_comp->support_33bits) {
+ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
+ if (ret) {
+ dev_err(&pdev->dev, "dma_set_mask return error.\n");
+ return ret;
+ }
+ }
+
ret = mtk_i2c_clock_enable(i2c);
if (ret) {
dev_err(&pdev->dev, "clock enable failed!\n");
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver.
2016-01-29 1:35 [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver Liguo Zhang
@ 2016-01-29 9:48 ` Daniel Kurtz
2016-01-29 9:50 ` Yingjoe Chen
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Daniel Kurtz @ 2016-01-29 9:48 UTC (permalink / raw)
To: Liguo Zhang
Cc: Wolfram Sang, srv_heupstream, Matthias Brugger, Eddie Huang,
Xudong Chen, Sascha Hauer, Linux I2C,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
moderated list:ARM/Mediatek SoC support
On Fri, Jan 29, 2016 at 9:35 AM, Liguo Zhang <liguo.zhang@mediatek.com> wrote:
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver.
2016-01-29 1:35 [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver Liguo Zhang
2016-01-29 9:48 ` Daniel Kurtz
@ 2016-01-29 9:50 ` Yingjoe Chen
2016-01-29 9:58 ` kbuild test robot
2016-01-29 10:23 ` kbuild test robot
3 siblings, 0 replies; 5+ messages in thread
From: Yingjoe Chen @ 2016-01-29 9:50 UTC (permalink / raw)
To: Liguo Zhang
Cc: Wolfram Sang, Xudong Chen, srv_heupstream, Sascha Hauer,
linux-kernel, linux-mediatek, linux-i2c, Matthias Brugger,
Eddie Huang, linux-arm-kernel
On Fri, 2016-01-29 at 09:35 +0800, Liguo Zhang wrote:
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
nit: enabled
However, after looking at it longer, the commit message doesn't make
much sense to me.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
> ---
> change in v3:
> Only inline the computation of reg_4g_mode in mtk_i2c_set_4g_mode().
> change in v2:
> Define a static inline funtion mtk_i2c_set_4g_mode() for support 4g mode.
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 42 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index aec8e6c..3c484f0 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -60,6 +60,7 @@
> #define I2C_DMA_INT_FLAG_NONE 0x0000
> #define I2C_DMA_CLR_FLAG 0x0000
> #define I2C_DMA_HARD_RST 0x0002
> +#define I2C_DMA_4G_MODE 0x0001
>
> #define I2C_DEFAULT_SPEED 100000 /* hz */
> #define MAX_FS_MODE_SPEED 400000
> @@ -88,6 +89,8 @@ enum DMA_REGS_OFFSET {
> OFFSET_RX_MEM_ADDR = 0x20,
> OFFSET_TX_LEN = 0x24,
> OFFSET_RX_LEN = 0x28,
> + OFFSET_TX_4G_MODE = 0x54,
> + OFFSET_RX_4G_MODE = 0x58,
> };
>
> enum i2c_trans_st_rs {
> @@ -133,6 +136,7 @@ struct mtk_i2c_compatible {
> unsigned char dcm: 1;
> unsigned char auto_restart: 1;
> unsigned char aux_len_reg: 1;
> + unsigned char support_33bits: 1;
> };
>
> struct mtk_i2c {
> @@ -182,6 +186,7 @@ static const struct mtk_i2c_compatible mt6577_compat = {
> .dcm = 1,
> .auto_restart = 0,
> .aux_len_reg = 0,
> + .support_33bits = 0,
> };
>
> static const struct mtk_i2c_compatible mt6589_compat = {
> @@ -190,6 +195,7 @@ static const struct mtk_i2c_compatible mt6589_compat = {
> .dcm = 0,
> .auto_restart = 0,
> .aux_len_reg = 0,
> + .support_33bits = 0,
> };
>
> static const struct mtk_i2c_compatible mt8173_compat = {
> @@ -198,6 +204,7 @@ static const struct mtk_i2c_compatible mt8173_compat = {
> .dcm = 1,
> .auto_restart = 1,
> .aux_len_reg = 1,
> + .support_33bits = 1,
> };
>
> static const struct of_device_id mtk_i2c_of_match[] = {
> @@ -366,6 +373,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
> return 0;
> }
>
> +static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
> +{
> + return (addr & BIT(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
> +}
> +
#define BIT(nr) (1UL << (nr))
#define BIT_ULL(nr) (1ULL << (nr))
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
I think you should use BIT_ULL.
> static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> int num, int left_num)
> {
> @@ -373,6 +385,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> u16 start_reg;
> u16 control_reg;
> u16 restart_flag = 0;
> + u32 reg_4g_mode = 0;
unnecessary init.
Joe.C
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver.
2016-01-29 1:35 [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver Liguo Zhang
2016-01-29 9:48 ` Daniel Kurtz
2016-01-29 9:50 ` Yingjoe Chen
@ 2016-01-29 9:58 ` kbuild test robot
2016-01-29 10:23 ` kbuild test robot
3 siblings, 0 replies; 5+ messages in thread
From: kbuild test robot @ 2016-01-29 9:58 UTC (permalink / raw)
Cc: kbuild-all, Wolfram Sang, srv_heupstream, Matthias Brugger,
Eddie Huang, Xudong Chen, Sascha Hauer, linux-i2c, linux-kernel,
linux-arm-kernel, linux-mediatek, Liguo Zhang
[-- Attachment #1: Type: text/plain, Size: 2034 bytes --]
Hi Liguo,
[auto build test WARNING on wsa/i2c/for-next]
[also build test WARNING on v4.5-rc1 next-20160129]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Liguo-Zhang/i2c-mt8173-add-4GB-mode-support-in-i2c-driver/20160129-174005
base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux i2c/for-next
config: xtensa-allyesconfig (attached as .config)
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=xtensa
All warnings (new ones prefixed by >>):
drivers/i2c/busses/i2c-mt65xx.c: In function 'mtk_i2c_set_4g_mode':
>> drivers/i2c/busses/i2c-mt65xx.c:378:2: warning: left shift count >= width of type
return (addr & BIT(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
^
vim +378 drivers/i2c/busses/i2c-mt65xx.c
362 if (target_speed > MAX_FS_MODE_SPEED) {
363 /* Set the high speed mode register */
364 i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
365 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
366 (sample_cnt << 12) | (step_cnt << 8);
367 } else {
368 i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0);
369 /* Disable the high speed transaction */
370 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
371 }
372
373 return 0;
374 }
375
376 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
377 {
> 378 return (addr & BIT(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
379 }
380
381 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
382 int num, int left_num)
383 {
384 u16 addr_reg;
385 u16 start_reg;
386 u16 control_reg;
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 44066 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver.
2016-01-29 1:35 [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver Liguo Zhang
` (2 preceding siblings ...)
2016-01-29 9:58 ` kbuild test robot
@ 2016-01-29 10:23 ` kbuild test robot
3 siblings, 0 replies; 5+ messages in thread
From: kbuild test robot @ 2016-01-29 10:23 UTC (permalink / raw)
Cc: kbuild-all, Wolfram Sang, srv_heupstream, Matthias Brugger,
Eddie Huang, Xudong Chen, Sascha Hauer, linux-i2c, linux-kernel,
linux-arm-kernel, linux-mediatek, Liguo Zhang
[-- Attachment #1: Type: text/plain, Size: 2214 bytes --]
Hi Liguo,
[auto build test WARNING on wsa/i2c/for-next]
[also build test WARNING on v4.5-rc1 next-20160129]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Liguo-Zhang/i2c-mt8173-add-4GB-mode-support-in-i2c-driver/20160129-174005
base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux i2c/for-next
config: i386-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
In file included from include/linux/kernel.h:10:0,
from include/linux/clk.h:16,
from drivers/i2c/busses/i2c-mt65xx.c:15:
drivers/i2c/busses/i2c-mt65xx.c: In function 'mtk_i2c_set_4g_mode':
include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
#define BIT(nr) (1UL << (nr))
^
>> drivers/i2c/busses/i2c-mt65xx.c:378:17: note: in expansion of macro 'BIT'
return (addr & BIT(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
^
vim +/BIT +378 drivers/i2c/busses/i2c-mt65xx.c
362 if (target_speed > MAX_FS_MODE_SPEED) {
363 /* Set the high speed mode register */
364 i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
365 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
366 (sample_cnt << 12) | (step_cnt << 8);
367 } else {
368 i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0);
369 /* Disable the high speed transaction */
370 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
371 }
372
373 return 0;
374 }
375
376 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
377 {
> 378 return (addr & BIT(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
379 }
380
381 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
382 int num, int left_num)
383 {
384 u16 addr_reg;
385 u16 start_reg;
386 u16 control_reg;
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 53452 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-01-29 10:21 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2016-01-29 1:35 [PATCH v3] i2c: mt8173: add 4GB mode support in i2c driver Liguo Zhang
2016-01-29 9:48 ` Daniel Kurtz
2016-01-29 9:50 ` Yingjoe Chen
2016-01-29 9:58 ` kbuild test robot
2016-01-29 10:23 ` kbuild test robot
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