From mboxrd@z Thu Jan  1 00:00:00 1970
From: Wolfram Sang <wsa@the-dreams.de>
Subject: Re: [PATCHv3 2/2] i2c: cadence: Implement save restore
Date: Sat, 12 Mar 2016 16:02:36 +0100
Message-ID: <20160312150236.GA1661@katana>
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To: Shubhrajyoti Datta <shubhrajyoti.datta@gmail.com>
Cc: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>, linux-i2c@vger.kernel.org, anirudh@xilinx.com, =?utf-8?B?U8O2cmVu?= Brinkmann <soren.brinkmann@xilinx.com>, Michal Simek <michal.simek@xilinx.com>, Shubhrajyoti Datta <shubhraj@xilinx.com>


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> >> zynq-mp has the capability of going off.
> >> the current kernel does not hit off however some day it will.
> >> since the overhead of having the support is not much may be it is bett=
er to have it in the kernel.
> >
> > This sounds like the patch is not tested?
> to simulate the suspend behavior I  did a reset of the module by writing =
to
> slcr register.
> And then did a transfer.

I'd prefer a patch which is tested under the actual condition. So, let's
wait until proper suspend support is added.

> >> +static void cdns_i2c_init(struct cdns_i2c *id)
> >> +{
> >> +     cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);
> >> +     /*
> >> +      * Cadence I2C controller has a bug wherein it generates
> >> +      * invalid read transaction after HW timeout in master receiver =
mode.
> >> +      * HW timeout is not used by this driver and the interrupt is di=
sabled.
> >> +      * But the feature itself cannot be disabled. Hence maximum value
> >> +      * is written to this register to reduce the chances of error.
> >> +      */
> >> +     cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET=
);
> >> +}
> >
> > This...
>=20
> Writes the values to the register.
>=20
> >
> >> +
> >> +/**
> >>   * cdns_i2c_runtime_resume - Runtime resume
> >>   * @dev:     Address of the platform_device structure
> >>   *
> >> @@ -853,6 +874,7 @@ static int __maybe_unused cdns_i2c_runtime_resume(=
struct device *dev)
> >>               dev_err(dev, "Cannot enable clock.\n");
> >>               return ret;
> >>       }
> >> +     cdns_i2c_init(xi2c);
> >
> > and this...
> At resume .
> (Actually this could be conditional however since we have 2 registers
> so can be unconditioal)
> >
> >> -
> >> -     /*
> >> -      * Cadence I2C controller has a bug wherein it generates
> >> -      * invalid read transaction after HW timeout in master receiver =
mode.
> >> -      * HW timeout is not used by this driver and the interrupt is di=
sabled.
> >> -      * But the feature itself cannot be disabled. Hence maximum value
> >> -      * is written to this register to reduce the chances of error.
> >> -      */
> >> -     cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET=
);
> >> +     cdns_i2c_init(id);
>=20
> And at init.

I understand what it does, but I don't see any connection to the
caching mentioned in the subject. So, this is maybe a seperate patch or
the commit message must be updated.


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