Re: [PATCH v2] i2c: bcm2835: Model Divider in CCF

Annaliese McDermond
2019-05-29T04:32:29Z

> On May 28, 2019, at 8:01 PM, Annaliese McDermond <nh6z@nh6z.net> wrote:
>
>
>
>> On May 28, 2019, at 12:52 AM, Stefan Wahren <stefan.wahren@i2se.com> wrote:

>> Please also check the output of /sys/kernel/debug/clk/clk_summary
>
> They’ll come up with the same name in the current code in the debug
> output. I agree this is mildly confusing and I’ll spin another version
> of the patch to give them unique clock names in clk_summary.

In v3 of the patch the output of /sys/kernel/debug/clk/clk_summary looks like the
following with two i2c devices enabled on the RPi. Note 3f804000.i2c_div and
3f205000.i2c_div.

enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
otg 0 0 0 480000000 0 0 50000
osc 7 7 4 19200000 0 0 50000
gp2 1 1 1 32768 0 0 50000
tsens 1 1 1 1920000 0 0 50000
vec 0 0 0 19200000 0 0 50000
otp 0 0 0 4800000 0 0 50000
timer 0 0 0 1000002 0 0 50000
pllh 4 4 0 855000000 0 0 50000
pllh_pix_prediv 1 1 0 855000000 0 0 50000
pllh_pix 0 0 0 85500000 0 0 50000
pllh_aux 1 1 0 3339844 0 0 50000
pllh_rcal_prediv 1 1 0 3339844 0 0 50000
pllh_rcal 0 0 0 333984 0 0 50000
plld 3 3 1 2000000024 0 0 50000
plld_dsi1 0 0 0 7812501 0 0 50000
plld_dsi0 0 0 0 7812501 0 0 50000
plld_per 4 4 3 500000006 0 0 50000
pcm 1 1 1 1535999 0 0 50000
gp0 1 1 1 24999389 0 0 50000
pll 1 1 0 98303848 0 0 50000
codec_clkin 2 2 0 98303848 0 0 50000
nadc 1 1 0 12287981 0 0 50000
madc 1 1 0 6143991 0 0 50000
ndac 1 1 0 12287981 0 0 50000
mdac 2 2 0 6143991 0 0 50000
bdiv 1 1 0 1535998 0 0 50000
gp1 1 1 1 24000094 0 0 50000
hsm 0 0 0 163682866 0 0 50000
uart 0 0 0 47999625 0 0 50000
plld_core 2 2 0 500000006 0 0 50000
sdram 0 0 0 166666668 0 0 50000
pllc 3 3 1 2400000000 0 0 50000
pllc_per 1 1 0 1200000000 0 0 50000
emmc 0 0 0 200000000 0 0 50000
pllc_core2 0 0 0 9375000 0 0 50000
pllc_core1 0 0 0 9375000 0 0 50000
pllc_core0 2 2 1 1200000000 0 0 50000
vpu 3 3 2 400000000 0 0 50000
3f804000.i2c_div 1 1 1 100000 0 0 50000
3f205000.i2c_div 1 1 1 100000 0 0 50000
aux_spi2 0 0 0 400000000 0 0 50000
aux_spi1 0 0 0 400000000 0 0 50000
aux_uart 0 0 0 400000000 0 0 50000
peri_image 0 0 0 400000000 0 0 50000
pllb 2 2 0 2800000012 0 0 50000
pllb_arm 1 1 0 1400000006 0 0 50000
plla 2 2 0 2400000000 0 0 50000
plla_ccp2 0 0 0 9375000 0 0 50000
plla_dsi0 0 0 0 9375000 0 0 50000
plla_per 0 0 0 9375000 0 0 50000
plla_core 1 1 0 1200000000 0 0 50000
h264 0 0 0 300000000 0 0 50000
isp 0 0 0 300000000 0 0 50000
v3d 0 0 0 300000000 0 0 50000
sc16is752_clk 1 1 0 1843200 0 0 50000
dsi1p 0 0 0 0 0 0 50000
dsi0p 0 0 0 0 0 0 50000
dsi1e 0 0 0 0 0 0 50000
dsi0e 0 0 0 0 0 0 50000
cam1 0 0 0 0 0 0 50000
cam0 0 0 0 0 0 0 50000
dpi 0 0 0 0 0 0 50000
tec 0 0 0 0 0 0 50000
smi 0 0 0 0 0 0 50000
slim 0 0 0 0 0 0 50000
dft 0 0 0 0 0 0 50000
aveo 0 0 0 0 0 0 50000
pwm 0 0 0 0 0 0 50000

--
Annaliese McDermond
nh6z@nh6z.net